Hi, We have a new board we just designed, and we're trying to fire up the first one. http://www.panoramio.com/photo/60806547 It has an Altera EP2AGX45DF29C5N on board; says so right on the label. When we hook up the JTAG USB Blaster pod and run the Quartus Programmer program, it insists that the chip is a GX65 so it doesn't allow us to load a configuration that was compiled for a GX45. What the heck? Any ideas? John
Altera FPGA weirdness
Started by ●October 18, 2011
Reply by ●October 18, 20112011-10-18
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:408s97p0dudngepc626tcgbcdu13qsqlt7@4ax.com...> Hi, > > We have a new board we just designed, and we're trying to fire up the > first one. > > http://www.panoramio.com/photo/60806547 > > It has an Altera EP2AGX45DF29C5N on board; says so right on the label. > > When we hook up the JTAG USB Blaster pod and run the Quartus > Programmer program, it insists that the chip is a GX65 so it doesn't > allow us to load a configuration that was compiled for a GX45. > > What the heck? Any ideas? > > John >Missing pull up/down ? I would suspect some Jtag interference with a new device. Do you have the latest Quartus 10 ? Or even the latest usb blaster driver? Cheers
Reply by ●October 19, 20112011-10-19
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:408s97p0dudngepc626tcgbcdu13qsqlt7@4ax.com...> Hi, > > We have a new board we just designed, and we're trying to fire up the > first one. > > http://www.panoramio.com/photo/60806547 > > It has an Altera EP2AGX45DF29C5N on board; says so right on the label. > > When we hook up the JTAG USB Blaster pod and run the Quartus > Programmer program, it insists that the chip is a GX65 so it doesn't > allow us to load a configuration that was compiled for a GX45. > > What the heck? Any ideas? > > John >Do you have TCK daisy chained with other devices? It's possible that you have a signal integrity problem on it. This is a fast-edge clock like any other and needs to be treated as such. Can you tell if the other bits in the stream are correct? If you can read them, it would be good to compare them to the BSDL file to see if it's a bit error or if the device is really providing the unexpected value. You can get the BSDL file on the Altera website. Bob -- == All google group posts are automatically deleted due to spam ==
Reply by ●October 19, 20112011-10-19
> Do you have the latest Quartus 10 ?The latest one is 11.0sp1, update Your software if You didn't do this already.
Reply by ●October 19, 20112011-10-19
On 19.10.2011 4:15, John Larkin wrote:> It has an Altera EP2AGX45DF29C5N on board; says so right on the label. > > When we hook up the JTAG USB Blaster pod and run the Quartus > Programmer program, it insists that the chip is a GX65 so it doesn't > allow us to load a configuration that was compiled for a GX45.Have you checked these few signals mentioned in the manual. I had this problem once in the past. "If the device is in reset state, when the nCONFIG or nSTATUS signal is low, the device IDCODE might not be read correctly. To read the device IDCODE correctly, you must issue the IDCODE JTAG instruction only when the nSTATUS signal is high." --Kim
Reply by ●October 19, 20112011-10-19
On Wed, 19 Oct 2011 11:06:04 +0300, Kim Enkovaara <kim.enkovaara@iki.fi> wrote:>On 19.10.2011 4:15, John Larkin wrote: >> It has an Altera EP2AGX45DF29C5N on board; says so right on the label. >> >> When we hook up the JTAG USB Blaster pod and run the Quartus >> Programmer program, it insists that the chip is a GX65 so it doesn't >> allow us to load a configuration that was compiled for a GX45. > >Have you checked these few signals mentioned in the manual. I >had this problem once in the past. > >"If the device is in reset state, when the nCONFIG or nSTATUS signal is >low, the device IDCODE might not be read correctly. To read the device >IDCODE correctly, you must issue the IDCODE JTAG instruction only when >the nSTATUS signal is high." > >--KimKim, When you posted that, my reaction was "no, nobody could make the jtag handshake that stupid"... but they did! We wrote a stub program for our ARM processor to just pull up nCONFIG, and now the chip id's itself as a GX45. Thanks! If you're ever in San Francisco, expect free beer. John
Reply by ●October 19, 20112011-10-19
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:331u9712mmv9bmoe32nvhe388s68h746kc@4ax.com...> On Wed, 19 Oct 2011 11:06:04 +0300, Kim Enkovaara > <kim.enkovaara@iki.fi> wrote: > >>On 19.10.2011 4:15, John Larkin wrote: >>> It has an Altera EP2AGX45DF29C5N on board; says so right on the label. >>> >>> When we hook up the JTAG USB Blaster pod and run the Quartus >>> Programmer program, it insists that the chip is a GX65 so it doesn't >>> allow us to load a configuration that was compiled for a GX45. >> >>Have you checked these few signals mentioned in the manual. I >>had this problem once in the past. >> >>"If the device is in reset state, when the nCONFIG or nSTATUS signal is >>low, the device IDCODE might not be read correctly. To read the device >>IDCODE correctly, you must issue the IDCODE JTAG instruction only when >>the nSTATUS signal is high." >> >>--Kim > > Kim, > > When you posted that, my reaction was "no, nobody could make the jtag > handshake that stupid"... but they did! > > We wrote a stub program for our ARM processor to just pull up nCONFIG, > and now the chip id's itself as a GX45. > > Thanks! > > If you're ever in San Francisco, expect free beer. > > John >Me too! I'm doing a Stratix V design now. I already have pullups on nConfig and nStatus, but it's great to know about this...ahhh...feature. Thanks, Kim! Bob -- == All google group posts are automatically deleted due to spam ==
Reply by ●October 19, 20112011-10-19
John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:>On Wed, 19 Oct 2011 11:06:04 +0300, Kim Enkovaara ><kim.enkovaara@iki.fi> wrote: > >>On 19.10.2011 4:15, John Larkin wrote: >>> It has an Altera EP2AGX45DF29C5N on board; says so right on the label. >>> >>> When we hook up the JTAG USB Blaster pod and run the Quartus >>> Programmer program, it insists that the chip is a GX65 so it doesn't >>> allow us to load a configuration that was compiled for a GX45. >> >>Have you checked these few signals mentioned in the manual. I >>had this problem once in the past. >> >>"If the device is in reset state, when the nCONFIG or nSTATUS signal is >>low, the device IDCODE might not be read correctly. To read the device >>IDCODE correctly, you must issue the IDCODE JTAG instruction only when >>the nSTATUS signal is high." >> >>--Kim > >Kim, > >When you posted that, my reaction was "no, nobody could make the jtag >handshake that stupid"... but they did!Isn't it possible to load the FPGA using an SPI like interface? I avoid using JTAG whenever I can. A JTAG interface is not something that is required for a device to function properly so it gets very little attention to get it right. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------
Reply by ●October 19, 20112011-10-19
On Wed, 19 Oct 2011 18:49:30 GMT, nico@puntnl.niks (Nico Coesel) wrote:>John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: > >>On Wed, 19 Oct 2011 11:06:04 +0300, Kim Enkovaara >><kim.enkovaara@iki.fi> wrote: >> >>>On 19.10.2011 4:15, John Larkin wrote: >>>> It has an Altera EP2AGX45DF29C5N on board; says so right on the label. >>>> >>>> When we hook up the JTAG USB Blaster pod and run the Quartus >>>> Programmer program, it insists that the chip is a GX65 so it doesn't >>>> allow us to load a configuration that was compiled for a GX45. >>> >>>Have you checked these few signals mentioned in the manual. I >>>had this problem once in the past. >>> >>>"If the device is in reset state, when the nCONFIG or nSTATUS signal is >>>low, the device IDCODE might not be read correctly. To read the device >>>IDCODE correctly, you must issue the IDCODE JTAG instruction only when >>>the nSTATUS signal is high." >>> >>>--Kim >> >>Kim, >> >>When you posted that, my reaction was "no, nobody could make the jtag >>handshake that stupid"... but they did! > >Isn't it possible to load the FPGA using an SPI like interface? I >avoid using JTAG whenever I can. A JTAG interface is not something >that is required for a device to function properly so it gets very >little attention to get it right.The ARM processor will load the FPGA through its SPI port in real life, but we're using JTAG to test the PCI Express interface parts first, because it's quick and easy. When it works. The production system has the ARM boot its code off a serial flash chip. Then it reads more of that flash chip and configures the FPGA. We'll probably compress the config data, because it's something insane like 30 megabits, mostly zeroes. John
Reply by ●October 19, 20112011-10-19
> > The ARM processor will load the FPGA through its SPI port in real > life, but we're using JTAG to test the PCI Express interface parts > first, because it's quick and easy. When it works. > > The production system has the ARM boot its code off a serial flash > chip. Then it reads more of that flash chip and configures the FPGA. > We'll probably compress the config data, because it's something insane > like 30 megabits, mostly zeroes. > > John > >I thought Quartus will compress for you ??? Do you need all 30 Mbits ???
