D-Type Flip flop with negated Q in Webise for a schematic capture

Sorry for the naive question, but how do I capture a schematic with a D 
and J-K FF that do have negated Q? I tried to draw the schematic with 
WebISE 13.3 and there is not such a thing readily available.
TIA.

Giuseppe Marullo

You might be more likely to get an answer if you post this question at the
Xilinx forums, for example:
http://forums.xilinx.com/t5/Design-Entry/bd-p/DEENBD
	   
					
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On Dec 12, 3:32=A0am, Giuseppe Marullo
<giuseppe.marullonos...@iname.com> wrote:
> Sorry for the naive question, but how do I capture a schematic with a D
> and J-K FF that do have negated Q? I tried to draw the schematic with
> WebISE 13.3 and there is not such a thing readily available.
> TIA.
>
> Giuseppe Marullo

Use an inverter on the clock net. It will get absorbed into the FFs.

Andy

Hi,

Giuseppe Marullo skrev 2011-12-12 10:32:
> Sorry for the naive question, but how do I capture a schematic with a D
> and J-K FF that do have negated Q? I tried to draw the schematic with
> WebISE 13.3 and there is not such a thing readily available.
> TIA.
>
> Giuseppe Marullo
When you run P&R the optimizing will reduce your design whenever 
possible. Check the output of the build process and see what it says.

Or make a very tiny design then you can see in fpga_editor what the P&R 
did do.


/michael

On Dec 12, 6:51=A0am, Andy <jonesa...@comcast.net> wrote:
> On Dec 12, 3:32=A0am, Giuseppe Marullo
>
> <giuseppe.marullonos...@iname.com> wrote:
> > Sorry for the naive question, but how do I capture a schematic with a D
> > and J-K FF that do have negated Q? I tried to draw the schematic with
> > WebISE 13.3 and there is not such a thing readily available.
> > TIA.
>
> > Giuseppe Marullo
>
> Use an inverter on the clock net. It will get absorbed into the FFs.
>
> Andy

The OP asked for a "negated Q", which I would interpert as being an
invertor on the Q output and not on the CLK input.

Ed McGettigan
--
Xilinx Inc.

Ed McGettigan <ed.mcgettigan@xilinx.com> wrote:

(snip, someone wrote)
>> Use an inverter on the clock net. It will get absorbed into the FFs.

> The OP asked for a "negated Q", which I would interpert as being an
> invertor on the Q output and not on the CLK input.

In any case, the inverter should be absorbed where possible,
and included elsewhere.

In the TTL days, it was usual for FF's to have Q and Qbar outputs,
with no extra inverter delay in the Qbar case.  

But even more, the OP didn't ask about the logic, but how to
draw it.  (Even though I don't especially like schematic capture.)

I suppose the schematic capture tools could add a Qbar output and
generate an inverter.   Maybe they allow for inverting outputs by
adding circles.  It is a tools question, not a logic question.

-- glen

> adding circles.  It is a tools question, not a logic question.
>
> -- glen
Glen, exactly. I need to do the capture thing because it is not so 
trivial to convert the schematic into verilog at first glance, and the 
FF uses both Q and Qbar. I was thinking it was a fault from my 
understanding of the tool, but qbar are missing on all FF i found in the 
tool.

The other way would it be to write a custom block where inside a verilog 
would implement the desired FF but maybe there is a simpler way.

Giuseppe Marullo

On 12/12/2011 12:45 PM, RCIngham wrote:
> You might be more likely to get an answer if you post this question at the
> Xilinx forums, for example:
> http://forums.xilinx.com/t5/Design-Entry/bd-p/DEENBD
Touche! I have posted the same question there.

On 12/12/2011 04:31 PM, Giuseppe Marullo wrote:
>> adding circles. It is a tools question, not a logic question.
>>
>> -- glen
> Glen, exactly. I need to do the capture thing because it is not so
> trivial to convert the schematic into verilog at first glance, and the
> FF uses both Q and Qbar. I was thinking it was a fault from my
> understanding of the tool, but qbar are missing on all FF i found in the
> tool.
>
> The other way would it be to write a custom block where inside a verilog
> would implement the desired FF but maybe there is a simpler way.
>
> Giuseppe Marullo
>
If you are going to be using schematic entry, then it is quite easy to
build all the primitives you need out of simpler primitives and make
a custom library of them.  I still do this on some CPLD interface
projects where simple definitions in schematic form are more concise.
I build N-way tristate buffers and tristate FFs and such that way.

Jon

Giuseppe Marullo <giuseppe.marullonospam@iname.com> wrote:
>> adding circles.  It is a tools question, not a logic question.

> Glen, exactly. I need to do the capture thing because it is not so 
> trivial to convert the schematic into verilog at first glance, and the 
> FF uses both Q and Qbar. 

Personally, I think I can write verilog faster than I can get
the lines drawn for schematic capture, but others may be different.

> I was thinking it was a fault from my understanding of the tool, 
> but qbar are missing on all FF i found in the tool.

For FPGAs, inverters will usually be moved into the logic before
or after, changing bits in the appropriate LUT.  So no delay difference.

That wasn't true in TTL.  So, now the reason for them is gone,
and the tools don't support them.

> The other way would it be to write a custom block where inside a verilog 
> would implement the desired FF but maybe there is a simpler way.

On some, you can draw your own symbol, including the circles.

-- glen