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Verilog module in VHDL project - ISE 13

Started by Mike Harrison January 3, 2012
I want to use the Xilinx Spartan-6 XAPP495 HDMI/DVI transmit/receive modules, which are written in
Verilog,  in a new VHDL project, as I'm much more familiar with VHDL - I don't do enough FPGA stuff
to justify the time to learn a new language for one project.

Can anyone point me towards how I can  include the verilog modules and make the signals visible to
my VHDL - any example of a verilog module included in a VHDL project would probably give me enough
to go on.

Mike Harrison wrote:
> I want to use the Xilinx Spartan-6 XAPP495 HDMI/DVI transmit/receive modules, which are written in > Verilog, in a new VHDL project, as I'm much more familiar with VHDL - I don't do enough FPGA stuff > to justify the time to learn a new language for one project. > > Can anyone point me towards how I can include the verilog modules and make the signals visible to > my VHDL - any example of a verilog module included in a VHDL project would probably give me enough > to go on. >
The simplest way is using the ISE NAvigator GUI. Add the verilog source file to the project. Then highlight the file in the Hierarchy window (clik once) and in the design process window you should see "View HDL instantiation template." In a VHDL project, the template should default to VHDL, but if for some reason it shows up in Verilog, you can change the properties for "View HDL Instantiation Template" by right clicking and there is a drop-down menu to select the language. The VHDL template will contain the entity declaration as well as an instantiation template. -- Gabor