Hi folks, I seem to have convinced ISE to output incorrect multiple-driver error messages. I've reduced the example to the following: -- test.vhd library ieee; use ieee.std_logic_1164.all; entity Test is port( Clock : in std_ulogic; Foo : out std_ulogic; Bar : out std_ulogic); end entity Test; architecture Arch of Test is begin Foo <= '1'; Bar <= '1'; process(Clock) is variable Temp : std_ulogic := '0'; begin if rising_edge(Clock) then Temp := not Temp; end if; Bar <= Temp; end process; end architecture Arch; -- test.prj vhdl work test.vhd -- test.xst run -ifn test.prj -ofn test.ngc -p xc6slx9-tqg144-2 -top test -opt_level 1 -opt_mode speed -arch arch $ xst -ifn test.xst Release 13.4 - xst O.87xd (lin64) [snip] Elaborating entity <Test> (architecture <Arch>) from library <work>. ERROR:HDLCompiler:1401 - "/tmp/vhdl/test.vhd" Line 16: Signal Foo in unit Test is connected to following multiple drivers: ERROR:HDLCompiler:1379 - "/tmp/vhdl/test.vhd" Line 13: Driver 0: output signal of instance Power ERROR:HDLCompiler:1379 - "/tmp/vhdl/test.vhd" Line 16: Driver 1: output signal Temp of instance Flip-Flop but clearly the signal with multiple drivers is Bar, not Foo! Thoughts on this? Chris
Xilinx ISE Multiple Drivers Error
Started by ●May 17, 2012
Reply by ●May 17, 20122012-05-17
>Hi folks, >I seem to have convinced ISE to output incorrect multiple-driver error >messages. I've reduced the example to the following: > >-- test.vhd >library ieee; >use ieee.std_logic_1164.all; > >entity Test is > port( > Clock : in std_ulogic; > Foo : out std_ulogic; > Bar : out std_ulogic); >end entity Test; > >architecture Arch of Test is >begin > Foo <= '1'; > Bar <= '1'; > > process(Clock) is > variable Temp : std_ulogic := '0'; > begin > if rising_edge(Clock) then > Temp := not Temp; > end if; > Bar <= Temp; > end process; >end architecture Arch; > >-- test.prj >vhdl work test.vhd > >-- test.xst >run >-ifn test.prj >-ofn test.ngc >-p xc6slx9-tqg144-2 >-top test >-opt_level 1 >-opt_mode speed >-arch arch > >$ xst -ifn test.xst >Release 13.4 - xst O.87xd (lin64) >[snip] >Elaborating entity <Test> (architecture <Arch>) from library <work>. >ERROR:HDLCompiler:1401 - "/tmp/vhdl/test.vhd" Line 16: Signal Foo in >unit Test is connected to following multiple drivers: >ERROR:HDLCompiler:1379 - "/tmp/vhdl/test.vhd" Line 13: Driver 0: output >signal of instance Power ERROR:HDLCompiler:1379 - "/tmp/vhdl/test.vhd" >Line 16: Driver 1: output signal Temp of instance Flip-Flop > >but clearly the signal with multiple drivers is Bar, not Foo! > >Thoughts on this? > >Chris >Perhaps XST is confused by your clocked process not being a normal synthesizable style, because the signal assignment is outside of the 'if rising_edge' section. Garbage in, garbage out. --------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●May 17, 20122012-05-17
Le 17/05/2012 10:44, RCIngham a �crit :>> Hi folks, >> I seem to have convinced ISE to output incorrect multiple-driver error >> messages. I've reduced the example to the following: >> >> -- test.vhd >> library ieee; >> use ieee.std_logic_1164.all; >> >> entity Test is >> port( >> Clock : in std_ulogic; >> Foo : out std_ulogic; >> Bar : out std_ulogic); >> end entity Test; >> >> architecture Arch of Test is >> begin >> Foo<= '1'; >> Bar<= '1'; >> >> process(Clock) is >> variable Temp : std_ulogic := '0'; >> begin >> if rising_edge(Clock) then >> Temp := not Temp; >> end if; >> Bar<= Temp; >> end process; >> end architecture Arch;[...]> Perhaps XST is confused by your clocked process not being a normal > synthesizable style, because the signal assignment is outside of the 'if > rising_edge' section.I don't think so. I use this very often to output a variable, it works absolutely fine.> Garbage in, garbage out.Actually not. What I think happens is that XST reduces ("optimizes") foo and bar to a single signal, names it foo probably because it's the first declared, and the complains about the multiple drivers. Nicolas
Reply by ●May 17, 20122012-05-17
On May 17, 3:44=A0am, "RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:> >Hi folks, > >I seem to have convinced ISE to output incorrect multiple-driver error > >messages. I've reduced the example to the following: > > >-- test.vhd > >library ieee; > >use ieee.std_logic_1164.all; > > >entity Test is > > =A0 =A0port( > > =A0 =A0 =A0 =A0 =A0 =A0Clock : in std_ulogic; > > =A0 =A0 =A0 =A0 =A0 =A0Foo : out std_ulogic; > > =A0 =A0 =A0 =A0 =A0 =A0Bar : out std_ulogic); > >end entity Test; > > >architecture Arch of Test is > >begin > > =A0 =A0Foo <=3D '1'; > > =A0 =A0Bar <=3D '1'; > > > =A0 =A0process(Clock) is > > =A0 =A0 =A0 =A0 =A0 =A0variable Temp : std_ulogic :=3D '0'; > > =A0 =A0begin > > =A0 =A0 =A0 =A0 =A0 =A0if rising_edge(Clock) then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Temp :=3D not Temp; > > =A0 =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0 =A0 =A0 =A0 =A0Bar <=3D Temp; > > =A0 =A0end process; > >end architecture Arch; > > >-- test.prj > >vhdl work test.vhd > > >-- test.xst > >run > >-ifn test.prj > >-ofn test.ngc > >-p xc6slx9-tqg144-2 > >-top test > >-opt_level 1 > >-opt_mode speed > >-arch arch > > >$ xst -ifn test.xst > >Release 13.4 - xst O.87xd (lin64) > >[snip] > >Elaborating entity <Test> (architecture <Arch>) from library <work>. > >ERROR:HDLCompiler:1401 - "/tmp/vhdl/test.vhd" Line 16: Signal Foo in > >unit Test is connected to following multiple drivers: > >ERROR:HDLCompiler:1379 - "/tmp/vhdl/test.vhd" Line 13: Driver 0: output > >signal of instance Power ERROR:HDLCompiler:1379 - "/tmp/vhdl/test.vhd" > >Line 16: Driver 1: output signal Temp of instance Flip-Flop > > >but clearly the signal with multiple drivers is Bar, not Foo! > > >Thoughts on this? > > >Chris > > Perhaps XST is confused by your clocked process not being a normal > synthesizable style, because the signal assignment is outside of the 'if > rising_edge' section. > > Garbage in, garbage out. > > --------------------------------------- > Posted throughhttp://www.FPGARelated.com- Hide quoted text - > > - Show quoted text -This style (assigning a signal from a variable after the clocked end- if, in a clocked process) is shown in an example in IEEE 1076.6-2004, IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis. If XST has a problem with that, it is a bug. Like Nicolas, I use this all the time. I rarely use a signal except for inter-process communications, and this is how I drive signals from my processes. Andy
Reply by ●May 17, 20122012-05-17
On May 16, 11:15=A0pm, Christopher Head <ch...@is.invalid> wrote:> Hi folks, > I seem to have convinced ISE to output incorrect multiple-driver error > messages. I've reduced the example to the following: > > -- test.vhd > library ieee; > use ieee.std_logic_1164.all; > > entity Test is > =A0 =A0 =A0 =A0 port( > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Clock : in std_ulogic; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Foo : out std_ulogic; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Bar : out std_ulogic); > end entity Test; > > architecture Arch of Test is > begin > =A0 =A0 =A0 =A0 Foo <=3D '1'; > =A0 =A0 =A0 =A0 Bar <=3D '1'; > > =A0 =A0 =A0 =A0 process(Clock) is > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 variable Temp : std_ulogic :=3D '0'; > =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if rising_edge(Clock) then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Temp :=3D not Temp; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Bar <=3D Temp; > =A0 =A0 =A0 =A0 end process; > end architecture Arch; > > -- test.prj > vhdl work test.vhd > > -- test.xst > run > -ifn test.prj > -ofn test.ngc > -p xc6slx9-tqg144-2 > -top test > -opt_level 1 > -opt_mode speed > -arch arch > > $ xst -ifn test.xst > Release 13.4 - xst O.87xd (lin64) > [snip] > Elaborating entity <Test> (architecture <Arch>) from library <work>. > ERROR:HDLCompiler:1401 - "/tmp/vhdl/test.vhd" Line 16: Signal Foo in > unit Test is connected to following multiple drivers: > ERROR:HDLCompiler:1379 - "/tmp/vhdl/test.vhd" Line 13: Driver 0: output > signal of instance Power ERROR:HDLCompiler:1379 - "/tmp/vhdl/test.vhd" > Line 16: Driver 1: output signal Temp of instance Flip-Flop > > but clearly the signal with multiple drivers is Bar, not Foo! > > Thoughts on this? > > ChrisThe problem is that you are assigning a value to the signal "Bar" in two different sections of your code and each of these will have a driver. The first one is in the architecture section: Bar <=3D '1'; The second one is in a process section: Bar <=3D Temp; You need to get rid of the first assignment and if you want to have a reset value then you should code this in your process section. I am assuming that you did not simulate this code because if you had it would show a 'U' state when the value of Temp is a '0' and in conflict with the permanent assignment of '1'. Note; 2nd post try as Google ate my 1st try. Ed McGettigan -- Xilinx Inc.
Reply by ●May 17, 20122012-05-17
Le 17/05/2012 14:09, Andy a �crit :> This style (assigning a signal from a variable after the clocked end- > if, in a clocked process) is shown in an example in IEEE 1076.6-2004, > IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis. > > If XST has a problem with that, it is a bug.I confirm that XST doesn't have any problem with it. Nicolas
Reply by ●May 18, 20122012-05-18
On Thu, 17 May 2012 09:04:58 -0700 (PDT) Ed McGettigan <ed.mcgettigan@xilinx.com> wrote:> On May 16, 11:15 pm, Christopher Head <ch...@is.invalid> wrote:[snip]> > $ xst -ifn test.xst > > Release 13.4 - xst O.87xd (lin64) > > [snip] > > Elaborating entity <Test> (architecture <Arch>) from library <work>. > > ERROR:HDLCompiler:1401 - "/tmp/vhdl/test.vhd" Line 16: Signal Foo in > > unit Test is connected to following multiple drivers: > > ERROR:HDLCompiler:1379 - "/tmp/vhdl/test.vhd" Line 13: Driver 0: > > output signal of instance Power ERROR:HDLCompiler:1379 - > > "/tmp/vhdl/test.vhd" Line 16: Driver 1: output signal Temp of > > instance Flip-Flop > > > > but clearly the signal with multiple drivers is Bar, not Foo! > > > > Thoughts on this? > > > > Chris > > The problem is that you are assigning a value to the signal "Bar" in > two different sections of your code and each of these will have a > driver. >[snip] Yes, of course that's the problem with the original code. The issue here is that XST isn't complaining about Bar: it's complaining about Foo, which has only a single driver! Chris
Reply by ●May 18, 20122012-05-18
On Thu, 17 May 2012 11:15:52 +0200 Nicolas Matringe <nicolas.matringe@fre.fre> wrote:> What I think happens is that XST reduces ("optimizes") foo and bar to > a single signal, names it foo probably because it's the first > declared, and the complains about the multiple drivers. > > NicolasI think this may have hit the nail on the head. I tried changing the constant assigned to Foo from '1' to '0', so that now the concurrent assignments were of different values, and the error message properly changed to complain about Bar. Chris
Reply by ●May 19, 20122012-05-19
On May 18, 5:51=A0pm, Christopher Head <ch...@is.invalid> wrote:> On Thu, 17 May 2012 09:04:58 -0700 (PDT) > > > > > > Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > On May 16, 11:15=A0pm, Christopher Head <ch...@is.invalid> wrote: > [snip] > > > $ xst -ifn test.xst > > > Release 13.4 - xst O.87xd (lin64) > > > [snip] > > > Elaborating entity <Test> (architecture <Arch>) from library <work>. > > > ERROR:HDLCompiler:1401 - "/tmp/vhdl/test.vhd" Line 16: Signal Foo in > > > unit Test is connected to following multiple drivers: > > > ERROR:HDLCompiler:1379 - "/tmp/vhdl/test.vhd" Line 13: Driver 0: > > > output signal of instance Power ERROR:HDLCompiler:1379 - > > > "/tmp/vhdl/test.vhd" Line 16: Driver 1: output signal Temp of > > > instance Flip-Flop > > > > but clearly the signal with multiple drivers is Bar, not Foo! > > > > Thoughts on this? > > > > Chris > > > The problem is that you are assigning a value to the signal "Bar" in > > two different sections of your code and each of these will have a > > driver. > > [snip] > > Yes, of course that's the problem with the original code. The issue > here is that XST isn't complaining about Bar: it's complaining about > Foo, which has only a single driver! > > Chris- Hide quoted text - > > - Show quoted text -Sorry, I missed the Foo vs Bar part of your orignal post. Which FPGA Family were you using? Ed McGettigan -- Xilinx Inc.
Reply by ●May 19, 20122012-05-19
On May 18, 5:51=A0pm, Christopher Head <ch...@is.invalid> wrote:> On Thu, 17 May 2012 09:04:58 -0700 (PDT) > > > > > > Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > On May 16, 11:15=A0pm, Christopher Head <ch...@is.invalid> wrote: > [snip] > > > $ xst -ifn test.xst > > > Release 13.4 - xst O.87xd (lin64) > > > [snip] > > > Elaborating entity <Test> (architecture <Arch>) from library <work>. > > > ERROR:HDLCompiler:1401 - "/tmp/vhdl/test.vhd" Line 16: Signal Foo in > > > unit Test is connected to following multiple drivers: > > > ERROR:HDLCompiler:1379 - "/tmp/vhdl/test.vhd" Line 13: Driver 0: > > > output signal of instance Power ERROR:HDLCompiler:1379 - > > > "/tmp/vhdl/test.vhd" Line 16: Driver 1: output signal Temp of > > > instance Flip-Flop > > > > but clearly the signal with multiple drivers is Bar, not Foo! > > > > Thoughts on this? > > > > Chris > > > The problem is that you are assigning a value to the signal "Bar" in > > two different sections of your code and each of these will have a > > driver. > > [snip] > > Yes, of course that's the problem with the original code. The issue > here is that XST isn't complaining about Bar: it's complaining about > Foo, which has only a single driver! > > Chris- Hide quoted text - > > - Show quoted text -Sorry, I missed the distinction between Foo and Bar in the original post. Which FPGA family were you using? Note: 3rd post attempt due to Google eating the first two. Ed McGettigan -- Xilinx Inc.
