Logic Glitches in Spartan-3?

I've got a 24-input AND gate that I'd like to avoid having add another
register delay to before I toss it across a clock boundary.

	all_done <= and_reduce(done);

If I just do it, AND it all together without a flop on the output, does
anyone know whether I'll get transition glitches (an output of 1 when
not all inputs are 1)?

I seem to remember something about individual LUTs being glitch-free,
and the synthesizer has to compose my giant AND out of either a LUT
tree or a mess o' LUTs "wire-and" driving a carry chain,  Offhand, it
seems like neither structure should glitch.  "Try it and see" doesn't
work; testing all 2^24 combinations and trying to determine whether I
get a glitch would be a beast of an effort.

Anyone know offhand?

-- 
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.

On May 23, 7:34=A0pm, Rob Gaddi <rga...@technologyhighland.invalid>
wrote:
> I've got a 24-input AND gate that I'd like to avoid having add another
> register delay to before I toss it across a clock boundary.
>
> =A0 =A0 =A0 =A0 all_done <=3D and_reduce(done);
>
> If I just do it, AND it all together without a flop on the output, does
> anyone know whether I'll get transition glitches (an output of 1 when
> not all inputs are 1)?
>
> I seem to remember something about individual LUTs being glitch-free,
> and the synthesizer has to compose my giant AND out of either a LUT
> tree or a mess o' LUTs "wire-and" driving a carry chain, =A0Offhand, it
> seems like neither structure should glitch. =A0"Try it and see" doesn't
> work; testing all 2^24 combinations and trying to determine whether I
> get a glitch would be a beast of an effort.
>
> Anyone know offhand?
>
> --
> Rob Gaddi, Highland Technology --www.highlandtechnology.com
> Email address domain is currently out of order. =A0See above to fix.

I believe the glitch free behavior of a LUT is from a single input
changing which results in the same value being output from two
different configuration FFs in the LUT.

But how would an AND gate glitch?  I guess if one input is at a zero
and other inputs change you are concerned that a one might sneak
through?  That is what the LUTs (at least according to Xilinx) are
assured to prevent.  If you are worried about multiple inputs
switching simultaneously, e.g. a 1 to a 0 and a 0 to a 1, that is a
race condition and there are no guarantees.  It just depends on which
gets to the output first.

Rick

Rob Gaddi <rgaddi@technologyhighland.invalid> wrote:
> I've got a 24-input AND gate that I'd like to avoid having add another
> register delay to before I toss it across a clock boundary.

>        all_done <= and_reduce(done);

> If I just do it, AND it all together without a flop on the output, does
> anyone know whether I'll get transition glitches (an output of 1 when
> not all inputs are 1)?

> I seem to remember something about individual LUTs being glitch-free,

That is the idea, though only true when the actual logic is
glitch-free. As you note, if one input is 0, for any combination
of other inputs the output should be zero. Note that does NOT
naturally happen for a SRAM. 

> and the synthesizer has to compose my giant AND out of either a LUT
> tree or a mess o' LUTs "wire-and" driving a carry chain,  Offhand, it
> seems like neither structure should glitch.  "Try it and see" doesn't
> work; testing all 2^24 combinations and trying to determine whether I
> get a glitch would be a beast of an effort.

It seems to me that a tree of glitch-free LUTs is glitch-free,
but see what others say.

Note that you might have different delays on the routes to different
inputs. In that case, depending on timing, there might be times
when all inputs are 1, and the output goes to 1. That is a race
condition, not a glitch.

-- glen

In article <jpk3g1$pmp$1@speranza.aioe.org>,
 glen herrmannsfeldt <gah@ugcs.caltech.edu> writes:

>It seems to me that a tree of glitch-free LUTs is glitch-free,
>but see what others say.

I don't think so.

Consider this example:
  LUT1 is OR(LUT2, LUT3)
  LUT2 is XOR(A, 0)
  LUT3 is XOR(A, 1)

In the static case, it doesn't matter what A is.
Now switch A.  With appropraite routing delays you can make a glitch.

-- 
These are my opinions.  I hate spam.

On Thursday, May 24, 2012 11:34:26 AM UTC+12, Rob Gaddi wrote:
> I've got a 24-input AND gate that I'd like to avoid having add another
> register delay to before I toss it across a clock boundary.

 A 24 wide and, is an unusual Clock Mux, and Glitches usually only bother a design if they are on a clock tree. Is this clocking something ?

 So long as the wide-AND output meets your clock domain Tsu.Th, why are you worried about glitches ? 

"Rob Gaddi" <rgaddi@technologyhighland.invalid> wrote in message 
news:20120523163426.7e77de05@rg.highlandtechnology.com...
> seems like neither structure should glitch.  "Try it and see" doesn't
> work; testing all 2^24 combinations and trying to determine whether I
> get a glitch would be a beast of an effort.

Doesn't seem it should be that difficult. 2^24 is only 16 million, not all 
that large compared with the 100's of MHz clocks. 

>"Rob Gaddi" <rgaddi@technologyhighland.invalid> wrote in message 
>news:20120523163426.7e77de05@rg.highlandtechnology.com...
>> seems like neither structure should glitch.  "Try it and see" doesn't
>> work; testing all 2^24 combinations and trying to determine whether I
>> get a glitch would be a beast of an effort.
>
>Doesn't seem it should be that difficult. 2^24 is only 16 million, not all

>that large compared with the 100's of MHz clocks. 
>
>
And the most important part of that can be done by a walking-zero test:
Start with all zero.
Then all one.
24-stage walking-zero.
All one.
All zero.
	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Hal Murray <hal-usenet@ip-64-139-1-69.sjc.megapath.net> wrote:
> In article <jpk3g1$pmp$1@speranza.aioe.org>,

(snip, I wrote)
>>It seems to me that a tree of glitch-free LUTs is glitch-free,
>>but see what others say.

> I don't think so.

> Consider this example:
>  LUT1 is OR(LUT2, LUT3)
>  LUT2 is XOR(A, 0)
>  LUT3 is XOR(A, 1)

> In the static case, it doesn't matter what A is.
> Now switch A.  With appropraite routing delays you can make 
> a glitch.

But note that I specifically excluded ones that depend on
timing delays, but you snipped out that part.

Note that non-LUT logic can glitch with timing delays, so
that is nothing new. 

Depending on design, LUT logic can glitch even in cases where 
gates wouldn't, which is why FPGAs use glitch-free LUTs. 

-- glen

j.m.granville@gmail.com wrote:
> On Thursday, May 24, 2012 11:34:26 AM UTC+12, Rob Gaddi wrote:
>> I've got a 24-input AND gate that I'd like to avoid having add another
>> register delay to before I toss it across a clock boundary.
> 
>  A 24 wide and, is an unusual Clock Mux, and Glitches usually only bother a design if they are on a clock tree. Is this clocking something ?
> 
>  So long as the wide-AND output meets your clock domain Tsu.Th, why are you worried about glitches ? 

Maybe you missed the fact that he's crossing clock domains, so there's
no way to ensure setup and hold time.

The walking 0's case is really the worst case for an AND gate.  It
guarantees glitches if your inputs aren't set up to "break
before make".  i.e. if you go from 1110111 to 1101111 without
going to 1100111 in between, you'll get a glitch if there
are enough routing delay differences to pass through the LUT.
You'll need to walk the zeroes in all directions to ensure
complete timing test coverage.  This means 276 transitions
for the 24-bit case (combination of 24 taken 2 at a time).
If your input logic can guarantee that you'll never make this
sort of state transition, then you won't get glitches.  I
think it would be easier to add another register after the
AND gate and then you just need to meet Tsu and Th.

- Gabor

Gabor <gabor@szakacs.invalid> wrote:
> j.m.granville@gmail.com wrote:
>> On Thursday, May 24, 2012 11:34:26 AM UTC+12, Rob Gaddi wrote:
>>> I've got a 24-input AND gate that I'd like to avoid having add another
>>> register delay to before I toss it across a clock boundary.
 
>>  A 24 wide and, is an unusual Clock Mux, and Glitches usually 
>> only bother a design if they are on a clock tree. Is this 
>> clocking something ?

> Maybe you missed the fact that he's crossing clock domains, 
> so there's no way to ensure setup and hold time.

That is true, but if there aren't any glitches it will go 1
either one cycle or the next.

> The walking 0's case is really the worst case for an AND gate.  
> It guarantees glitches if your inputs aren't set up to "break
> before make".  i.e. if you go from 1110111 to 1101111 without
> going to 1100111 in between, you'll get a glitch if there
> are enough routing delay differences to pass through the LUT.

Given that it is an AND of done bits, in the usual case each
one transitions from 0 to 1 until all are 1. 

If you use a traditional SRAM, with row select logic, the bits
of each row coming out, and then a MUX to select one of the
rows, even if the inputs change between states that don't
even come close to a cell of a different value, the output
can still glitch. The delays through different parts of
the DEMUX row select, or the MUX column select can be
different. Fill up a SRAM such that only one cell is 1, 
hold one input at 0, and go through all combinations of
the other inputs. 

For that matter, fill the array with all 0, and go through 
all combinations of inputs. An SRAM can still glitch to 1. 

The glitchless LUTs used in FPGAs are designed not to do that.

If you hold one input a 0, for all combinations of other inputs,
even with timing differences, the output should stay zero.

> You'll need to walk the zeroes in all directions to ensure
> complete timing test coverage.  This means 276 transitions
> for the 24-bit case (combination of 24 taken 2 at a time).
> If your input logic can guarantee that you'll never make this
> sort of state transition, then you won't get glitches.  I
> think it would be easier to add another register after the
> AND gate and then you just need to meet Tsu and Th.

Since the 24 bit AND will be generated as some number of
LUTs feeding either another LUT or carry chain AND logic,
another possibility is to put a register between the two
levels of AND. It seems to me that isn't necessary, but
could be done.

-- glen