Data transfers between MicroBlaze and VHDL

I am using EDK 14.1 and a Spartan-6 FPGA (potentially changing FPGAs
in the future to the Artix 7 or Kintex 7).  I am trying to figure out
a way that I could output the data from the MicroBlaze to a VHDL
module and also the reverse transfer.  This way I can capture the
data, use it in some calculations, and then also pass it back to the
MicroBlaze for further use.

I am new to Embedded Design and MicroBlaze, so any help that anyone
may have would be greatly appreciated.  If anyone has other options
for transferring data between the MicroBlaze and my VHDL modules, I am
looking for something that would allow me to transfer data using a 32-
bit wide bus at the fastest speed the FPGA will allow me to clock at.

- Robert

>I am using EDK 14.1 and a Spartan-6 FPGA (potentially changing FPGAs
>in the future to the Artix 7 or Kintex 7).  I am trying to figure out
>a way that I could output the data from the MicroBlaze to a VHDL
>module and also the reverse transfer.  This way I can capture the
>data, use it in some calculations, and then also pass it back to the
>MicroBlaze for further use.
>
>I am new to Embedded Design and MicroBlaze, so any help that anyone
>may have would be greatly appreciated.  If anyone has other options
>for transferring data between the MicroBlaze and my VHDL modules, I am
>looking for something that would allow me to transfer data using a 32-
>bit wide bus at the fastest speed the FPGA will allow me to clock at.
>
>- Robert
>

All you need to do is create a custom AXI IP module that will interface
between your IP and the Microblaze. There is a wizard that will do this for
you.

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On Tuesday, June 19, 2012 4:27:27 PM UTC-4, maxascent wrote:
> >I am using EDK 14.1 and a Spartan-6 FPGA (potentially changing FPGAs
> >in the future to the Artix 7 or Kintex 7).  I am trying to figure out
> >a way that I could output the data from the MicroBlaze to a VHDL
> >module and also the reverse transfer.  This way I can capture the
> >data, use it in some calculations, and then also pass it back to the
> >MicroBlaze for further use.
> >
> >I am new to Embedded Design and MicroBlaze, so any help that anyone
> >may have would be greatly appreciated.  If anyone has other options
> >for transferring data between the MicroBlaze and my VHDL modules, I am
> >looking for something that would allow me to transfer data using a 32-
> >bit wide bus at the fastest speed the FPGA will allow me to clock at.
> >
> >- Robert
> >
>=20
> All you need to do is create a custom AXI IP module that will interface
> between your IP and the Microblaze. There is a wizard that will do this f=
or
> you.
>=20
> Jon	  =20
> 				=09
> ---------------------------------------	=09
> Posted through http://www.FPGARelated.com



Thank you Jon for your reply, but I am still a little confused.  I have not=
iced that there are IP modules for BRAM, GPIO, and even FSL...but I am unsu=
re as to which one to choose.  I have tried adding the FSL IP module into m=
y design, but when I do, I don't see how to connect it to anything so that =
data can be transferred to and from the MicroBlaze?  Are there any helpful =
guides that you know of that could possibly walk me through some of these m=
ethods?

- Robert

On Wed, 20 Jun 2012 06:25:12 -0700, robert.higginbotham0 wrote:

> On Tuesday, June 19, 2012 4:27:27 PM UTC-4, maxascent wrote:
>> >I am using EDK 14.1 and a Spartan-6 FPGA (potentially changing FPGAs
>> >in the future to the Artix 7 or Kintex 7).  I am trying to figure out
>> >a way that I could output the data from the MicroBlaze to a VHDL
>> >module and also the reverse transfer.  This way I can capture the
>> >data, use it in some calculations, and then also pass it back to the
>> >MicroBlaze for further use.
>> >
>> >I am new to Embedded Design and MicroBlaze, so any help that anyone
>> >may have would be greatly appreciated.  If anyone has other options
>> >for transferring data between the MicroBlaze and my VHDL modules, I am
>> >looking for something that would allow me to transfer data using a 32-
>> >bit wide bus at the fastest speed the FPGA will allow me to clock at.
>> >
>> >- Robert
>> >
>> >
>> All you need to do is create a custom AXI IP module that will interface
>> between your IP and the Microblaze. There is a wizard that will do this
>> for you.
>> 
>> Jon
>> 					
>> ---------------------------------------
>> Posted through http://www.FPGARelated.com
> 
> 
> 
> Thank you Jon for your reply, but I am still a little confused.  I have
> noticed that there are IP modules for BRAM, GPIO, and even FSL...but I
> am unsure as to which one to choose.  I have tried adding the FSL IP
> module into my design, but when I do, I don't see how to connect it to
> anything so that data can be transferred to and from the MicroBlaze? 
> Are there any helpful guides that you know of that could possibly walk
> me through some of these methods?
> 
> - Robert

All I know about the Microblaze is that it's a synthesizable 
microprocessor, so take this with an appropriate-sized grain of salt:

I expect that the most convenient and commonly used way of connecting to 
the Microblaze core is going to be as a memory-mapped peripheral.  So at 
some point you need to learn how to make ports on your VHDL module appear 
to the Microblaze as a memory location (or you need to dig around and 
find out if there's a tutorial or wizard that will help you out).

Whether you want to configure things so that your interface has the 
Microblaze pounding away at one memory location, or several, or whether 
you want to augment the interface between the Microblaze and your logic 
with a bit of block RAM that's configured as dual-port memory, is a 
decision that you'll have to make.

Ultimately, though, I think the best way you have of making your logic go 
"zing!" in response to something the processor does is to have logic 
registers show up in the Microblaze's memory map.

-- 
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com

Robert,

Guessing from the limited details you provided, it sounds as if you are goi=
ng to be trading a reasonable amount of data between the microblaze and you=
r VHDL module.

GPIO is likely not sufficient. BRAM (dual port setup) may be possible, howe=
ver you would still need to implement the handshaking between the microblaz=
e and your VHDL module. FSL sounds like it may be a possible candidate or a=
t least give you an idea of how it can be done.

Check out the FSL core datasheet DS449 and the application note XAPP529. Th=
is should give you an idea in a general sense how it's done. From there you=
 should be able to arrive at what best suites the needs of your application=
.

Regards,
Carlton

What you need to do is to look at doing the tutorial that Xilinx provide
with EDK. Its called concepts tools and techniques. Basically Microblaze
can use either a PLB or AXI bus. The AXI bus is the newer standard and so
that one would be the best to use. Xilinx provide a wizard that creates an
interface bewteen the AXI bus and your IP. So you don't even have to know
how AXI works. You just get a set of standard signals which are a write and
read data path. But just have a look at some of the Xilinx docs as this
should make things clearer.

Jon 	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Thank you to everyone for your replies!  This gives me some great information to look over and figure this out.  Thanks again for your help!

- Robert



On Wednesday, June 20, 2012 3:00:28 PM UTC-4, maxascent wrote:
> What you need to do is to look at doing the tutorial that Xilinx provide
> with EDK. Its called concepts tools and techniques. Basically Microblaze
> can use either a PLB or AXI bus. The AXI bus is the newer standard and so
> that one would be the best to use. Xilinx provide a wizard that creates an
> interface bewteen the AXI bus and your IP. So you don't even have to know
> how AXI works. You just get a set of standard signals which are a write and
> read data path. But just have a look at some of the Xilinx docs as this
> should make things clearer.
> 
> Jon 	   
> 					
> ---------------------------------------		
> Posted through http://www.FPGARelated.com



On Wednesday, June 20, 2012 3:00:28 PM UTC-4, maxascent wrote:
> What you need to do is to look at doing the tutorial that Xilinx provide
> with EDK. Its called concepts tools and techniques. Basically Microblaze
> can use either a PLB or AXI bus. The AXI bus is the newer standard and so
> that one would be the best to use. Xilinx provide a wizard that creates an
> interface bewteen the AXI bus and your IP. So you don't even have to know
> how AXI works. You just get a set of standard signals which are a write and
> read data path. But just have a look at some of the Xilinx docs as this
> should make things clearer.
> 
> Jon 	   
> 					
> ---------------------------------------		
> Posted through http://www.FPGARelated.com

Carlton,

I have tried finding the XAPP529 pdf from Xilinx, but it always comes up wi=
th a "Bad encrypt dictionary" message.  Would you be able to email me the d=
ocument if you have it?  Also, I noticed in the FSL Core Datasheet (acquire=
d through XPS 14.1) that the FSL is not supported by the 7-Series FPGAs, si=
nce I am looking to migrate to that from my Spartan6, do you have another s=
uggestion/option for me in lieu of the FSL?

- Robert (robert.higginbotham0@gmail.com)

On Wednesday, June 20, 2012 1:27:47 PM UTC-4, carlt...@gmail.com wrote:
> Robert,
>=20
> Guessing from the limited details you provided, it sounds as if you are g=
oing to be trading a reasonable amount of data between the microblaze and y=
our VHDL module.
>=20
> GPIO is likely not sufficient. BRAM (dual port setup) may be possible, ho=
wever you would still need to implement the handshaking between the microbl=
aze and your VHDL module. FSL sounds like it may be a possible candidate or=
 at least give you an idea of how it can be done.
>=20
> Check out the FSL core datasheet DS449 and the application note XAPP529. =
This should give you an idea in a general sense how it's done. From there y=
ou should be able to arrive at what best suites the needs of your applicati=
on.
>=20
> Regards,
> Carlton

On Jun 21, 2:44=A0pm, RHigginbotham <robert.higginboth...@gmail.com>
wrote:
> Carlton,
>
> I have tried finding the XAPP529 pdf from Xilinx, but it always comes up =
with a "Bad encrypt dictionary" message. =A0Would you be able to email me t=
he document if you have it? =A0Also, I noticed in the FSL Core Datasheet (a=
cquired through XPS 14.1) that the FSL is not supported by the 7-Series FPG=
As, since I am looking to migrate to that from my Spartan6, do you have ano=
ther suggestion/option for me in lieu of the FSL?
>
> - Robert (robert.higginboth...@gmail.com)
>
>
>
>
>
>
>
> On Wednesday, June 20, 2012 1:27:47 PM UTC-4, carlt...@gmail.com wrote:
> > Robert,
>
> > Guessing from the limited details you provided, it sounds as if you are=
 going to be trading a reasonable amount of data between the microblaze and=
 your VHDL module.
>
> > GPIO is likely not sufficient. BRAM (dual port setup) may be possible, =
however you would still need to implement the handshaking between the micro=
blaze and your VHDL module. FSL sounds like it may be a possible candidate =
or at least give you an idea of how it can be done.
>
> > Check out the FSL core datasheet DS449 and the application note XAPP529=
. This should give you an idea in a general sense how it's done. From there=
 you should be able to arrive at what best suites the needs of your applica=
tion.
>
> > Regards,
> > Carlton

I think that message is usually an indication that your reader is not
sufficiently current.  Try updating and opening the document again.

Rick

RHigginbotham <robert.higginbotham0@gmail.com> writes:

> Carlton,
>
> I have tried finding the XAPP529 pdf from Xilinx, but it always comes
> up with a "Bad encrypt dictionary" message.  Would you be able to
> email me the document if you have it?  Also, I noticed in the FSL Core
> Datasheet (acquired through XPS 14.1) that the FSL is not supported by
> the 7-Series FPGAs, since I am looking to migrate to that from my
> Spartan6, do you have another suggestion/option for me in lieu of the
> FSL?
>

AXI4-stream replaces FSL.  The AXI docs are in UG761.

As an aside - you might want to install the DocNav from Xilinx - that
keeps all their docs together and updated:

http://myfpgablog.blogspot.co.uk/2011/03/xilinx-document-navigator-is-live.html



Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware