Trying to remember how to use Quartus

I would like to compile my new design to get a baseline number for
resource usage.  I have done this before, but I don't remember how to
set up VHDL component libraries using Quartus.  I have a common and a
hardware library and a couple of VHDL source files for each.  I can't
find a way to associate the source files with the particular libraries. 
In Modelsim you just create the library and make the connection in the
GUI.  I can create a library in Quartus, but I can't find a way to
connect this to a source file.  I am also not sure that this is the same
as a VHDL library.  

The help files seem to skirt around this issue... any advice? 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

rickman <spamgoeshere4@yahoo.com> wrote in message news:<40D8A954.C61855BA@yahoo.com>...
> I would like to compile my new design to get a baseline number for
> resource usage.  I have done this before, but I don't remember how to
> set up VHDL component libraries using Quartus.  I have a common and a
> hardware library and a couple of VHDL source files for each.  I can't
> find a way to associate the source files with the particular libraries. 
> In Modelsim you just create the library and make the connection in the
> GUI.  I can create a library in Quartus, but I can't find a way to
> connect this to a source file.  I am also not sure that this is the same
> as a VHDL library.  
> 
> The help files seem to skirt around this issue... any advice? 

Rick,

1. set up user libraries under "Settings".  Its a little different between
QII v3.0 and QII v4.0. Overall I'm happier with 4.0.  That's Assignments>
Settings>User Libraries

2. I often add scattered files directly using Project>Add/Remove files, with
component defs in a separate package.  File order does matter.

Hope this helps,
-rajeev-

Rajeev, should have answered your question. There are two things to be aware
of:

1. The default file search order is the current project directory followed
by the library paths specified in the Assignment ->Settings-.User Libraries
dialog.

2. The important thing to note is that File Order is important for VHDL
elaboration or you will see missing entity messages. You can use the Up,
Down buttons in the Project->Add Files Dialog to organize the order in which
theVHDL files will be elaborated. The ones on the top are elaborated first
and the entities discovered can be referenced by files lower on the list.

Hope this helps.

- Subroto Datta
Altera Corp.

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:40D8A954.C61855BA@yahoo.com...
> I would like to compile my new design to get a baseline number for
> resource usage.  I have done this before, but I don't remember how to
> set up VHDL component libraries using Quartus.  I have a common and a
> hardware library and a couple of VHDL source files for each.  I can't
> find a way to associate the source files with the particular libraries.
> In Modelsim you just create the library and make the connection in the
> GUI.  I can create a library in Quartus, but I can't find a way to
> connect this to a source file.  I am also not sure that this is the same
> as a VHDL library.
>
> The help files seem to skirt around this issue... any advice?
>
> -- 
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX

Subroto Datta wrote:
> 
> Rajeev, should have answered your question. There are two things to be aware
> of:
> 
> 1. The default file search order is the current project directory followed
> by the library paths specified in the Assignment ->Settings-.User Libraries
> dialog.
> 
> 2. The important thing to note is that File Order is important for VHDL
> elaboration or you will see missing entity messages. You can use the Up,
> Down buttons in the Project->Add Files Dialog to organize the order in which
> theVHDL files will be elaborated. The ones on the top are elaborated first
> and the entities discovered can be referenced by files lower on the list.

Thanks, but no, this does not help.  I have already added the libraries
using the settings dialog.  But I don't know how to connect the VHDL
package files to the library.  I think I am missing something basic to
how this works.  In modelsim, you just create a library, say "common",
and then click on each file that goes into that library and change its
association to link it to the library.  I gather that Quartus work
rather differently?  Do I need to separately compile the library sources
or something?  

I have two user libraries; common and hardware; with two source files
each and more may be added later.  BTW, I really can't find any info
about this in the help files.  There is info on how to write the VHDL,
but nothing that I can find on how to hook all this together.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

rickman wrote:

> In modelsim, you just create a library, say "common",
> and then click on each file that goes into that library and change its
> association to link it to the library.  I gather that Quartus work
> rather differently?  Do I need to separately compile the library sources
> or something?

Something.

Find the USE statements referencing the library.
If one says USE WORK.mystuff.ALL
then all the mystuff files must
either be in the WORK group with the other
sources or the group that they are in must
be mapped to WORK.

If your code says
 LIBRARY common;
 USE common.mystuff.ALL;
Then you must map the mystuff file collection 
to the identifier "common".

     -- Mike Treseler

Hi Rick,

  I think what you are asking for is how one can compile VHDL design units
into specific pre-compiled VHDL libraries - a feature supported by the VHDL
language and by simulation tools such as Modelsim.  The answer is in QII 4.0
and 4.1 we don't support this feature.  All user design units are compiled
into the work library.  To support designs that expect design units to live
in specific library names, we search the work library whenever we fail to
find a design unit in a library with the given name.  Consider this example:

library my_lib;
use my_lib.my_package.all;

In Modelsim, the user would compile his package my_package into the library
my_lib.  In Quartus II, we compile the package into the work library.
However, when we see the use clause, we notice that my_package doesn't live
in the library my_lib because no such library exists, so we look for
my_package in work.  Note that this makes it impossible for a user design to
refer to two packages of the same name.

- Subroto Datta
Altera Corp



"Mike Treseler" <mike_treseler@comcast.net> wrote in message
news:CI-dndp7T5EnzEfdRVn-tw@comcast.com...
> rickman wrote:
>
> > In modelsim, you just create a library, say "common",
> > and then click on each file that goes into that library and change its
> > association to link it to the library.  I gather that Quartus work
> > rather differently?  Do I need to separately compile the library sources
> > or something?
>
> Something.
>
> Find the USE statements referencing the library.
> If one says USE WORK.mystuff.ALL
> then all the mystuff files must
> either be in the WORK group with the other
> sources or the group that they are in must
> be mapped to WORK.
>
> If your code says
>  LIBRARY common;
>  USE common.mystuff.ALL;
> Then you must map the mystuff file collection
> to the identifier "common".
>
>      -- Mike Treseler

Mike Treseler wrote:
> 
> rickman wrote:
> 
> > In modelsim, you just create a library, say "common",
> > and then click on each file that goes into that library and change its
> > association to link it to the library.  I gather that Quartus work
> > rather differently?  Do I need to separately compile the library sources
> > or something?
> 
> Something.
> 
> Find the USE statements referencing the library.
> If one says USE WORK.mystuff.ALL
> then all the mystuff files must
> either be in the WORK group with the other
> sources or the group that they are in must
> be mapped to WORK.
> 
> If your code says
>  LIBRARY common;
>  USE common.mystuff.ALL;
> Then you must map the mystuff file collection
> to the identifier "common".

Thanks for the advice.  That is how it is *supposed* to work and I could
not find the way to map the file containing "mystuff" to the library
"common".  Turns out that the Altera internal compiler does not support
this sort of library.  But it becomes mostly transparent because they
put all user entities and packages in the WORK library when they are
compiled and *always* looks for them in the WORK library regardless of
what your USE statement says.  

The only glitch this causes is when you have multiple packages with the
same name in different libraries.  With this approach they will clash.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX