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TMDS CML PCB

Started by inv___ October 28, 2012
Hello,

    I have problem with understanding differential nature of DC coupled CML
pair in TDMS (DVI, HDMI). In DC coupled LVDS current flows from source
through one wire of transmission line then through termination resistor and
goes back through second line to source. So currents are equal and they
flow in opposite direction. Loop is formed by source, differential pair and
termination resistor. In CML pair current flows only in one line at the
same time, second line is disconnected. If I have understood it good return
current has to flow in ground plane. Loop is formed by source, one line
from differential pair, termination resistor, VCC plane, decoupling
capacitor, ground plane. Does it make ground connection between for example
two PCBs extremely crucial? Does sending TMDS signal through twisted pair
CAT cable depends highly on good shield connection between systems because
this is conductor through which return currents flow ?

Best Regards,
inv___

	   
					
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inv___ <3827@embeddedrelated> wrote:
 
> I have problem with understanding differential nature of DC coupled CML > pair in TDMS (DVI, HDMI). In DC coupled LVDS current flows from source > through one wire of transmission line then through termination resistor and > goes back through second line to source. So currents are equal and they > flow in opposite direction. Loop is formed by source, differential pair and > termination resistor.
> In CML pair current flows only in one line at the > same time, second line is disconnected.
In TDMS, a line either changes state or not. But there are many signals in the cable, and it arranges the transitions such that over all the wires, an almost equal number transition in each direction. Well, that is from reading http://en.wikipedia.org/wiki/Transition-minimized_differential_signaling I didn't try counting all the combinations myself. For LVDS, it takes 2N wires to send N signals, where the two of a pair either change state or not. A lot of redundancy there. TDMS sends 8 signals in 10 wires, each of which is in a twisted pair. The code is designed to minimize the number of the 10 transitioning, and so that most are in opposite direction. If not all are opposite, the next unequal transition will be in the opposite direction. Enough current will flow through the ground wires to keep EM radiation down.
> If I have understood it good return > current has to flow in ground plane. Loop is formed by source, one line > from differential pair, termination resistor, VCC plane, decoupling > capacitor, ground plane. Does it make ground connection between for example > two PCBs extremely crucial? Does sending TMDS signal through twisted pair > CAT cable depends highly on good shield connection between systems because > this is conductor through which return currents flow ?
Even in that case, the decoupling capacitors would keep the signals away from the ground lines, but there would still be too much radiation. Since one idea behind TDMS is to minimize EM radiation, that doesn't seem likely. -- glen
line is disconnected. 
> >In TDMS, a line either changes state or not. But there are many signals >in the cable, and it arranges the transitions such that over all the >wires, an almost equal number transition in each direction. >Well, that is from reading > >http://en.wikipedia.org/wiki/Transition-minimized_differential_signaling
In specyfication of DVI I did not find anything that says that coding data in one channel depends on data in other channels. Could you point me where can I find how is it done ?
>I didn't try counting all the combinations myself. > >For LVDS, it takes 2N wires to send N signals, where the two of a pair >either change state or not. A lot of redundancy there. > >TDMS sends 8 signals in 10 wires, each of which is in a twisted pair. >The code is designed to minimize the number of the 10 transitioning, >and so that most are in opposite direction. If not all are opposite, >the next unequal transition will be in the opposite direction.
As I understood DVI specyfication there is one pair for reference clock (pixel clock) and three for data (cahnnels for color). 8b/10b is used thats true, but to code each octet in channel (additional 2 bits are used for marking type of xor operation, negation for DC balance or they are used for control signal coding, HSync, VSync). --------------------------------------- Posted through http://www.FPGARelated.com