Hi all, started to look into alternatives to Verilog and VHDL and stumbled over chisel from UCB: http://chisel.eecs.berkeley.edu/ Any experiences and comment on this language? Looks like some challenge for me as it involves practically learning 3 new languages at once: chisel itself, Scala on which it is based, and Verilog, which is produced (I'm used to VHDL). Cheers, Martin PS: I was *very* long absent from this group ;-)
Chisel as alternative HDL
Started by ●December 28, 2012
Reply by ●December 28, 20122012-12-28
"Martin Schoeberl" <martin@jopdesign.com> wrote in message news:1621424063378432030.694310martin-jopdesign.com@reader.albasani.net...> Hi all, > > started to look into alternatives to Verilog and VHDL and > stumbled over chisel from UCB: > http://chisel.eecs.berkeley.edu/ > > Any experiences and comment on this language? > > Looks like some challenge for me as it involves practically > learning 3 new languages at once: chisel itself, Scala on which > it is based, and Verilog, which is produced (I'm used to VHDL). > > Cheers, > Martin > > PS: I was *very* long absent from this group ;-) >You might find this interesting: http://www.myhdl.org
Reply by ●December 29, 20122012-12-29
"garyr" <garyr@fidalgo.net> wrote:> "Martin Schoeberl" <martin@jopdesign.com> wrote in message > news:1621424063378432030.694310martin-jopdesign.com@reader.albasani.net... >> Hi all, >> >> started to look into alternatives to Verilog and VHDL and >> stumbled over chisel from UCB: >> http://chisel.eecs.berkeley.edu/ >> >> Any experiences and comment on this language? >> >> Looks like some challenge for me as it involves practically >> learning 3 new languages at once: chisel itself, Scala on which >> it is based, and Verilog, which is produced (I'm used to VHDL). >> >> Cheers, >> Martin >> >> PS: I was *very* long absent from this group ;-) >> > > You might find this interesting: http://www.myhdl.orgThanks for pointing this out, although it was not the 'real' answer to my question ;-) I'm already looking at MyHDL and some other projects. chisel just lookes most promising at the moment. Maybe I change my mind. A good comparison would be to do one HW design, e.g. a standard MIPS pipeline, in all languages and compare the efficiency of the language and the efficiency of the resulting HW implementation. Martin
Reply by ●December 29, 20122012-12-29
Martin Schoeberl wrote:> A good comparison would be to do one HW design, e.g. a standard MIPS > pipeline, in all languages and compare the efficiency of the language and > the efficiency of the resulting HW implementation.MAN, that would be a landmark achievement! You might even go down in history as the author of "the Schoeberl paper". Even if it wouldn't change the (horrible) way I do designs now, it would sure be an interesting read. Jon
Reply by ●December 29, 20122012-12-29
On 12/28/12 11:25 PM, Martin Schoeberl wrote:> "garyr" <garyr@fidalgo.net> wrote: >> "Martin Schoeberl" <martin@jopdesign.com> wrote in message >> news:1621424063378432030.694310martin-jopdesign.com@reader.albasani.net... >>> Hi all, >>> >>> started to look into alternatives to Verilog and VHDL and >>> stumbled over chisel from UCB: >>> http://chisel.eecs.berkeley.edu/ >>> >>> Any experiences and comment on this language? >>> >>> Looks like some challenge for me as it involves practically >>> learning 3 new languages at once: chisel itself, Scala on which >>> it is based, and Verilog, which is produced (I'm used to VHDL). >>> >>> Cheers, >>> Martin >>> >>> PS: I was *very* long absent from this group ;-) >>> >> >> You might find this interesting: http://www.myhdl.org > > Thanks for pointing this out, although it was not the 'real' answer to > my question ;-) > > I'm already looking at MyHDL and some other projects. chisel just lookes > most promising at the moment. Maybe I change my mind. > > A good comparison would be to do one HW design, e.g. a standard MIPS > pipeline, in all languages and compare the efficiency of the language and > the efficiency of the resulting HW implementation. > > Martin >Typically to do a comparison you have to have an example/project fairly limited in scope. It is hard to realize the benefits with such small examples. A language might have a /nice/ description for example "A" but is horrible at parametrization or it can be difficult to connect many modules or fails miserably at example "B" and "C". I am not familiar with Chisel and Scala and cannot comment directly. I am familiar with MyHDL and I have used MyHDL successfully for commercial and independent projects. Regards, Chris
Reply by ●December 29, 20122012-12-29
Jon Elson <elson@pico-systems.com> wrote:> Martin Schoeberl wrote: > > >> A good comparison would be to do one HW design, e.g. a standard MIPS >> pipeline, in all languages and compare the efficiency of the language and >> the efficiency of the resulting HW implementation. > > MAN, that would be a landmark achievement! You might even go down > in history as the author of "the Schoeberl paper". Even if it wouldn't > change the (horrible) way I do designs now, it would sure be an > interesting read. > > JonMaybe I should tone this done. Yes, it would be nice to have this example. It would also be nice to have this comparison in a paper. Let's see where this leads. I will start on a smaller scale with simpler examples. Maybe up to a very simple processor that I already have in VHDL. Will keep you informed along the path. If anybody would like to join this effort we can setup a repository. Martin
Reply by ●December 30, 20122012-12-30
Martin Schoeberl wrote:> Jon Elson <elson@pico-systems.com> wrote: >> Martin Schoeberl wrote: >> >> >>> A good comparison would be to do one HW design, e.g. a standard MIPS >>> pipeline, in all languages and compare the efficiency of the language >>> and the efficiency of the resulting HW implementation. >> >> MAN, that would be a landmark achievement! You might even go down >> in history as the author of "the Schoeberl paper". Even if it wouldn't >> change the (horrible) way I do designs now, it would sure be an >> interesting read. >> >> Jon > > Maybe I should tone this done. Yes, it would be nice to have this example. > It would also be nice to have this comparison in a paper. Let's see where > this leads. > > I will start on a smaller scale with simpler examples. Maybe up to a very > simple processor that I already have in VHDL. Will keep you informed along > the > path. If anybody would like to join this effort we can setup a repository.Great, and thanks for putting in the effort! Even a VERY simple example of the same function in several languages could be quite instructive. But, a somewhat larger project would be more likely to expose some of the deficiencies of this or that language. Jon
Reply by ●December 31, 20122012-12-31
On 12/30/12 4:42 PM, Jon Elson wrote:> Martin Schoeberl wrote: > >> Jon Elson <elson@pico-systems.com> wrote: >>> Martin Schoeberl wrote: >>> >>> >>>> A good comparison would be to do one HW design, e.g. a standard MIPS >>>> pipeline, in all languages and compare the efficiency of the language >>>> and the efficiency of the resulting HW implementation. >>> >>> MAN, that would be a landmark achievement! You might even go down >>> in history as the author of "the Schoeberl paper". Even if it wouldn't >>> change the (horrible) way I do designs now, it would sure be an >>> interesting read. >>> >>> Jon >> >> Maybe I should tone this done. Yes, it would be nice to have this example. >> It would also be nice to have this comparison in a paper. Let's see where >> this leads. >> >> I will start on a smaller scale with simpler examples. Maybe up to a very >> simple processor that I already have in VHDL. Will keep you informed along >> the >> path. If anybody would like to join this effort we can setup a repository. > Great, and thanks for putting in the effort! > Even a VERY simple example of the same function in several languages > could be quite instructive. But, a somewhat larger project would > be more likely to expose some of the deficiencies of this or that > language. > > Jon >You might be interested in this rebuttal to a paper that compared a couple non-traditional HDLs. http://thread.gmane.org/gmane.comp.python.myhdl/2701 Regards, Chris
Reply by ●January 2, 20132013-01-02
Christopher Felton <abc@def.org> wrote:> On 12/30/12 4:42 PM, Jon Elson wrote: >> Martin Schoeberl wrote: >> >>> Jon Elson <elson@pico-systems.com> wrote: >>>> Martin Schoeberl wrote: >>>> >>>> >>>>> A good comparison would be to do one HW design, e.g. a standard MIPS >>>>> pipeline, in all languages and compare the efficiency of the language >>>>> and the efficiency of the resulting HW implementation. >>>> >>>> MAN, that would be a landmark achievement! You might even go down >>>> in history as the author of "the Schoeberl paper". Even if it wouldn't >>>> change the (horrible) way I do designs now, it would sure be an >>>> interesting read. >>>> >>>> Jon >>> >>> Maybe I should tone this done. Yes, it would be nice to have this example. >>> It would also be nice to have this comparison in a paper. Let's see where >>> this leads. >>> >>> I will start on a smaller scale with simpler examples. Maybe up to a very >>> simple processor that I already have in VHDL. Will keep you informed along >>> the >>> path. If anybody would like to join this effort we can setup a repository. >> Great, and thanks for putting in the effort! >> Even a VERY simple example of the same function in several languages >> could be quite instructive. But, a somewhat larger project would >> be more likely to expose some of the deficiencies of this or that >> language. >> >> Jon >> > > You might be interested in this rebuttal to a > paper that compared a couple non-traditional HDLs. > > http://thread.gmane.org/gmane.comp.python.myhdl/2701 > > Regards, > ChrisThis is definitely interesting, but the link is dead :-( Do you have the title of that paper so I can try to Google it. Cheers, Martin
Reply by ●January 3, 20132013-01-03
On 1/2/13 8:35 PM, Martin Schoeberl wrote:> Christopher Felton <abc@def.org> wrote: >> On 12/30/12 4:42 PM, Jon Elson wrote: >>> Martin Schoeberl wrote: >>> >>>> Jon Elson <elson@pico-systems.com> wrote: >>>>> Martin Schoeberl wrote: >>>>> >>>>> >>>>>> A good comparison would be to do one HW design, e.g. a standard MIPS >>>>>> pipeline, in all languages and compare the efficiency of the language >>>>>> and the efficiency of the resulting HW implementation. >>>>> >>>>> MAN, that would be a landmark achievement! You might even go down >>>>> in history as the author of "the Schoeberl paper". Even if it wouldn't >>>>> change the (horrible) way I do designs now, it would sure be an >>>>> interesting read. >>>>> >>>>> Jon >>>> >>>> Maybe I should tone this done. Yes, it would be nice to have this example. >>>> It would also be nice to have this comparison in a paper. Let's see where >>>> this leads. >>>> >>>> I will start on a smaller scale with simpler examples. Maybe up to a very >>>> simple processor that I already have in VHDL. Will keep you informed along >>>> the >>>> path. If anybody would like to join this effort we can setup a repository. >>> Great, and thanks for putting in the effort! >>> Even a VERY simple example of the same function in several languages >>> could be quite instructive. But, a somewhat larger project would >>> be more likely to expose some of the deficiencies of this or that >>> language. >>> >>> Jon >>> >> >> You might be interested in this rebuttal to a >> paper that compared a couple non-traditional HDLs. >> >> http://thread.gmane.org/gmane.comp.python.myhdl/2701 >> >> Regards, >> Chris > > This is definitely interesting, but the link is dead :-( > > Do you have the title of that paper so I can try to Google it. > > Cheers, > Martin >I believe this is the original paper: http://referaat.cs.utwente.nl/conference/17/paper/7344/comparing-hardware-description-languages.pdf But note the objections in the previous thread I posted. The comparisons are incomplete (comparing non-working HDL, the author(s) didn't learn enough of the languages). Regards, Chris
