Chisel as alternative HDL

On 2/14/2013 1:14 PM, jonesandy@comcast.net wrote:
> Chris,
>
> Do you ignore synthesis notes and warnings, or do you cross-check at least some of them?

No I don't ignore them, they are reviewed and certain ones
are interrogated if deemed important.  And determining if
they are important is decided by the design engineer,
same as you, they are aware of the design and "no problemo"
referring back to the original source, if needed.

>
> There are precious few efficient ways to confirm "completeness" of the design verification effort.
>
> I cross-check my synthesis warnings as a secondary confirmation that something is not missed either in the design or in the verification. I can usually tell from the warning, and knowledge of the design, whether it is a potential problem or is acceptable/expected. I do not modify the design to eliminate acceptable/expected warnings (that would require designing at too low a level of abstraction). It still takes a lot of time, but it has been very effective, not only as a secondary confirmation of verification, but also as an indication of where/not to improve performance or utilization to meet requirements.
>
> If I used an alternative HDL as source, then I'd have to trace the warnings I could not immediately resolve back through the intermediate code to the source. That takes more time, and from what I have seen, would not be offset by any improvmement in productivity provided by the alternative language.
>
> If I used verilog, I might have a different opinion.
>
> However, where other languages, perhaps including these alternative HDLs, may be more helpful is in the verification of the HDL design, regardless of the HDL used (traditional or alternative).
>
> Andy
>

In this case the alternative HDL used is MyHDL, and MyHDL
-in my experience- does not mangle the source enough to
prohibit tracing back.  As you indicated, it does have an
"elaboration" phase but this has not been an issue (tracing
back the generated VHDL or Verilog).

I agree, the alternative HDL (because they are typically
based on as general purpose high-level language) are ideal
for modeling and verification.  The V*s will always lag the
other languages for general features.

Regards,
Chris

On Saturday, 29 December 2012 00:06:20 UTC, Martin Schoeberl  wrote (with s=
lightly less compacted blank-lines than this):
> Hi all,
> started to look into alternatives to Verilog and VHDL and
> stumbled over chisel from UCB:
>=20
> http://chisel.eecs.berkeley.edu/
>=20
> Any experiences and comment on this language?
>
>=20
> Looks like some challenge for me as it involves practically
> learning 3 new languages at once: chisel itself, Scala on which
> it is based, and Verilog, which is produced (I'm used to VHDL).
>=20
> Cheers,
>=20
> Martin
>=20
> PS: I was *very* long absent from this group ;-)


I haven't seen mention of PSHDL (pshdl.org) which I have recently come acro=
ss via a talk at CCC (German conference), is this worthy of consideration a=
lso? Seems it is/can be converted into one of (/both?) the V* languages for=
 end-use and is aiming to make it easier to learn for beginners (like mysel=
f).

John.

Hi all,

I'm a Berkeley PhD student who has worked extensively with Chisel both 
in classes and research. I love it, though I did not have much 
experience with anything else before starting on it. A common 
description for Chisel I use is "hardware at the word level". It allows 
for n-dimensional arrays of hardware (wires, gates, modules, whatever). 
We call it a hardware construction language because it can generate an 
array of different architectures by changing the input parameters. 
Another benefit is the cycle-accurate C++ tester, which allows for fast 
design verification. You do need to learn Chisel and Scala, though they 
have many similarities. Learning Verilog isn't necessary unless you want 
to post-process the output for some reason. So maybe it involves only 
learning 1.5 new languages! There is no VHDL support, nor talk of 
including it.

To attempt remaining unbiased, I'd also like to mention MyHDL, which is 
an HDL built on Python (a language people are generally more familiar 
with). If your fear is learning new languages, this might be a good 
alternative. I know nothing about it save its existence.

Thanks!
Stevo



On 07/24/2014 10:07 AM, jgbreezer@gmail.com wrote:
> On Saturday, 29 December 2012 00:06:20 UTC, Martin Schoeberl  wrote (with slightly less compacted blank-lines than this):
>> Hi all,
>> started to look into alternatives to Verilog and VHDL and
>> stumbled over chisel from UCB:
>>
>> http://chisel.eecs.berkeley.edu/
>>
>> Any experiences and comment on this language?
>>
>>
>> Looks like some challenge for me as it involves practically
>> learning 3 new languages at once: chisel itself, Scala on which
>> it is based, and Verilog, which is produced (I'm used to VHDL).
>>
>> Cheers,
>>
>> Martin
>>
>> PS: I was *very* long absent from this group ;-)
>
>
> I haven't seen mention of PSHDL (pshdl.org) which I have recently come across via a talk at CCC (German conference), is this worthy of consideration also? Seems it is/can be converted into one of (/both?) the V* languages for end-use and is aiming to make it easier to learn for beginners (like myself).
>
> John.
>