FPGA for large HDMI switch

Matt,

This is not a question of practical/economic consideration, per your original statement. 

Altera Stratix V GX B series has 66 full-duplex, 14.1 Gbps transceivers with independent Rx/Tx PLLs (e.g. 66 inputs, 66 outputs), and 490K-952K logic elements for an x-bar. 

Probably not cost effective, but technically feasible.

Andy

On 23/04/13 01:36, jonesandy@comcast.net wrote:
> Matt,
> 
> This is not a question of practical/economic consideration, per your
> original statement.
> 
> Altera Stratix V GX B series has 66 full-duplex, 14.1 Gbps
> transceivers with independent Rx/Tx PLLs (e.g. 66 inputs, 66
> outputs), and 490K-952K logic elements for an x-bar.

I didn't realise the Rx and Tx sides of the transceivers could operate
independently - that's why I dismissed these as too small.

> 
> Probably not cost effective, but technically feasible.

Well, if it is possible to buy these devices, then I agree.

> 
> Andy
> 

Arrow shows 5SGXEB6R2F40C3N in stock @ $9,092.00 ea (min/multiple = 1).

Very likely not cost effective...

Andy

Not a fgpa solution, but have a look at analog devices ADN4605 and its 
likes.. A few of those and you got full matrix of even more ports. 

David Brown wrote:
> On 08/04/13 17:58, thomas.entner99@gmail.com wrote:
>> You might consider to use 16 external receivers and 16 external
>> transmitters and use the FPGA to mux the databuses. There are some
>> Rx/Tx that support DDR on the databuses, so this will get you 16pins
>> per Rx/TX (12b+HD+VD+DE+Clk) x 32 = 512 Pins Total. There are at
>> least low cost Cyclone IV that have so many IOs (CE30/CE40).
>>
>> But I have not checked if this DDR-style Rx/Tx are also available for
>> HDMI1.4 and how this solution compares to this crosspoint switches.
>>
>> Regards,
>>
>> Thomas
>>
> 
> Unfortunately, the numbers are bigger than that.  HDMI receivers and
> transmitters that I have seen have SDR on the databus, but for HDMI1.4
> that would be 36 lines at 340 Mbps.  So for 16 channels in and 16
> channels out, that would be 36*16*2 = 1152 pins, all running at 340
> Mbps.  That's a lot of pins - and even if we got an FPGA big enough,
> designing such a board and getting matched lengths on all the lines
> needed would be a serious effort.
> 
> The crosspoint switches mentioned by another poster are one likely
> choice.  The other realistic architecture is to use large numbers of
> 4-to-1 HDMI multiplexers.

Probably not a good solution at 340 Mbps, but when you have a large
parallel bus and need a number of these in a crossbar, you can split
the bus into bit slices and handle them in separate smaller and
much cheaper devices.  Generally, using a very high pin-count FPGA
with very little logic is a big waste of silicon.  For something as
regular in structure as a parallel-bus crossbar, splitting the bus
into slices can reduce the silicon area by using a number of FPGA's
programmed identically each handling the same slice from every port
on the crossbar.  The problem at very high speeds would be part to
part skew.  You can control voltage and temperature among the parts,
but you're at the mercy of the manufacturer for process variation.

-- 
Gabor

David Brown <david.brown@removethis.hesbynett.no> writes:

> needed, I don't think there are FPGA's big enough on the market.  Had

It's possible to build build a clos style crossbar out of smaller
FPGA's, but you "waste" a lot of serdes links for switch expansion, e.g.
in the figure below each switch element could be a 4x4 FPGA which is
interconnected to form a 8x8 switch:

http://upload.wikimedia.org/wikipedia/commons/c/c9/Benesnetwork.png

//Petter

-- 
.sig removed by request.