I am looking for a FPGA Development Board, with a FPGA that supports fully asynchronous RAMs. I know that Altera APEX20k supports fully asynchronous RAMs. Are there also Xilinx FPGAs that provide this functionality (large FPGAs like the APEX20K1000C or APEX20K1500E)? regards Gottfried
FPGA with fully asynchronous RAM
Started by ●June 30, 2004
Reply by ●June 30, 20042004-06-30
If you need small RAMs, sure! But small is the key word. The two types of memory in the Xilinx devices are BlockRAMs which require the clock for the read and CLB SelectRAM distributed memory. In the Virtex-II and Virtex-IIPro devices support up to 128 bit depth for single port memories or 64 bit for dual port. The memories can be any width, distributed throughout the logic fabric. While BlockRAMs are more efficient, supplying 18kbit chunks, they require a clock to get the read value. The CLB SelectRAMs are fully asynchronous read. You still need an edge for the write - the write pulse is generated internally from the supplied edge - but you have the asynchronous nature you just *have* to have. "Fuchs Gottfried" <fuchs@ecs.tuwien.ac.at> wrote in message news:40E2DB28.20501@ecs.tuwien.ac.at...> I am looking for a FPGA Development Board, with a FPGA that supports > fully asynchronous RAMs. I know that Altera APEX20k supports fully > asynchronous RAMs. > Are there also Xilinx FPGAs that provide this functionality (large FPGAs > like the APEX20K1000C or APEX20K1500E)? > > regards > Gottfried >
Reply by ●June 30, 20042004-06-30
Xilinx LUT-RAMs read asynchronously and write synchronously (clocked). Xilinx BlockRAMs perform read and write operations synchronously (clocked). In most situations, clocked operation is preferrable and inherently more reliable. Peter Alfke> From: Fuchs Gottfried <fuchs@ecs.tuwien.ac.at> > Newsgroups: comp.arch.fpga > Date: Wed, 30 Jun 2004 17:24:24 +0200 > Subject: FPGA with fully asynchronous RAM > > I am looking for a FPGA Development Board, with a FPGA that supports > fully asynchronous RAMs. I know that Altera APEX20k supports fully > asynchronous RAMs. > Are there also Xilinx FPGAs that provide this functionality (large FPGAs > like the APEX20K1000C or APEX20K1500E)? > > regards > Gottfried >
Reply by ●June 30, 20042004-06-30
Hi Gottfried, I assume you're talking about on chip RAM? If so, I respectfully suggest that you don't need asynchronous RAMs at all. What you do need to do is think harder about your application! You'll have a more robust solution if you keep everything synchronous. cheers, Syms. "Fuchs Gottfried" <fuchs@ecs.tuwien.ac.at> wrote in message news:40E2DB28.20501@ecs.tuwien.ac.at...> I am looking for a FPGA Development Board, with a FPGA that supports > fully asynchronous RAMs. I know that Altera APEX20k supports fully > asynchronous RAMs. > Are there also Xilinx FPGAs that provide this functionality (large FPGAs > like the APEX20K1000C or APEX20K1500E)? > > regards > Gottfried >
Reply by ●July 1, 20042004-07-01
I know that synchronous RAMs are preferable, but the asynchronous RAMs are needed in my design due to the fact that it is a processor design that is fully asynchronous. regards Gottfried Symon wrote:> Hi Gottfried, > I assume you're talking about on chip RAM? If so, I respectfully suggest > that you don't need asynchronous RAMs at all. What you do need to do is > think harder about your application! You'll have a more robust solution if > you keep everything synchronous. > cheers, Syms. > "Fuchs Gottfried" <fuchs@ecs.tuwien.ac.at> wrote in message > news:40E2DB28.20501@ecs.tuwien.ac.at... > >>I am looking for a FPGA Development Board, with a FPGA that supports >>fully asynchronous RAMs. I know that Altera APEX20k supports fully >>asynchronous RAMs. >>Are there also Xilinx FPGAs that provide this functionality (large FPGAs >>like the APEX20K1000C or APEX20K1500E)? >> >>regards >>Gottfried >> > > >
Reply by ●July 1, 20042004-07-01
Hi Gottfried, I don't know, you academics poisoning those kids' minds with your crazy plans! ;-) Just kidding, sounds like an interesting project, I wish you the best of luck with the timing tools provided by the FPGA manufacturers! cheers, Syms. "Fuchs Gottfried" <fuchs@ecs.tuwien.ac.at> wrote in message news:40E3C0E0.5040101@ecs.tuwien.ac.at...> I know that synchronous RAMs are preferable, but the asynchronous RAMs > are needed in my design due to the fact that it is a processor design > that is fully asynchronous. > > regards > Gottfried >
Reply by ●July 1, 20042004-07-01
"Fully asynchronous", ohmygod! Well, you can always generate a strobe pulse when you want to read or write. We would call that a clock, but if your religion forbids that, you can call it something else..We are agnostic, up to a point :-) Peter Alfke =================================================> From: "Symon" <symon_brewer@hotmail.com> > Newsgroups: comp.arch.fpga > Date: Thu, 1 Jul 2004 09:39:08 -0700 > Subject: Re: FPGA with fully asynchronous RAM > > Hi Gottfried, > I don't know, you academics poisoning those kids' minds with your crazy > plans! ;-) > Just kidding, sounds like an interesting project, I wish you the best of > luck with the timing tools provided by the FPGA manufacturers! > cheers, Syms. > "Fuchs Gottfried" <fuchs@ecs.tuwien.ac.at> wrote in message > news:40E3C0E0.5040101@ecs.tuwien.ac.at... >> I know that synchronous RAMs are preferable, but the asynchronous RAMs >> are needed in my design due to the fact that it is a processor design >> that is fully asynchronous. >> >> regards >> Gottfried >> > >
Reply by ●July 1, 20042004-07-01
In article <40E3C0E0.5040101@ecs.tuwien.ac.at>, Fuchs Gottfried <fuchs@ecs.tuwien.ac.at> wrote:>I know that synchronous RAMs are preferable, but the asynchronous RAMs >are needed in my design due to the fact that it is a processor design >that is fully asynchronous.I'm sorry for the pain you are going to suffer making self timing circuits in an FPGA. -- Nicholas C. Weaver nweaver@cs.berkeley.edu
Reply by ●July 15, 20042004-07-15
I'm not. FPGAs are specifically designed for synchronous logic designs. While an async design can be done if done very carefully, the lack of support for this by the tools makes it excruciating at best. Every once in a while someone comes along with the bright idea to use an FPGA as a platform for async logic experiments. A search of the literature should provide a trail of efforts that al come to the same conclusion: that the tools and FPGAs don't support it. There are plenty of academics that have already plowed this path. Read their work and be forewarned. Nicholas Weaver wrote:> In article <40E3C0E0.5040101@ecs.tuwien.ac.at>, > Fuchs Gottfried <fuchs@ecs.tuwien.ac.at> wrote: > >I know that synchronous RAMs are preferable, but the asynchronous RAMs > >are needed in my design due to the fact that it is a processor design > >that is fully asynchronous. > > I'm sorry for the pain you are going to suffer making self timing > circuits in an FPGA. > -- > Nicholas C. Weaver nweaver@cs.berkeley.edu-- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759
Reply by ●July 16, 20042004-07-16
Hi everybody, while you are discussing asynchronous designs on FPGAs... Has anybody made experience with the balsa tools? http://www.cs.man.ac.uk/apt/projects/tools/balsa/ And YES! todays FPGAs are designed to work synchronously, but there are asynchronous chips around (e.g. part of the SPARC 2i and other �P) that seem to work sufficently. So, while it's still hard work its not impossible to do.. My final question is...when will there be FPGAs with C-Elements etc. ?? (Small market at this time, I think :-) ) Ray Andraka <ray@andraka.com> wrote in message news:<40F7154E.794740D5@andraka.com>...> I'm not. FPGAs are specifically designed for synchronous logic designs. > While an async design can be done if done very carefully, the lack of support > for this by the tools makes it excruciating at best. Every once in a while > someone comes along with the bright idea to use an FPGA as a platform for > async logic experiments. A search of the literature should provide a trail of > efforts that al come to the same conclusion: that the tools and FPGAs don't > support it. There are plenty of academics that have already plowed this > path. Read their work and be forewarned. >
