Cascaded floating-point reduction?

Glen,

I know Synplify Pro has a retiing/pipelining option (for Xilinx and Altera =
targets), and I think Altera's and Xilinx's own tools do as well.

The last time I checked, straight retiming may only move logic into an adja=
cent clock cycle, but pipelining of functions such as multipliers or multip=
lexers can spread that logic over several clock cycles. I have seen example=
s where a large multiply (larger than a DSP block could handle) was automat=
ically partitioned and pipelined to use multiplie DSP blocks.=20

Since straight retiming may be limited to adjacent clock cycles, it might b=
e best to provide additional clock cycles of latency before and after the e=
xpression, so that two empty, adjacent clock cycles are available. Note tha=
t retiming does not need to have empty clock cycles to share logic across, =
but there does need to be positive slack in those adjacent clock cycles in =
order to "make room" for any retimed logic.

As far as timing or utiliszation is concerned, as long as I have positive s=
lack in both, with any margin requirements met, I prefer to have the most u=
nderstandable, maintainable description possible, even if a lesser descript=
ion would cut either (or both) by half. This was very hard to do when I sta=
rted VHDL based FPGA design many years ago (just meeting timing and utiliza=
tion was tougher in those devices and with those tools, and the "optimizer"=
 in me was hard to re-calibrate.) I now try to optimize for maintainability=
 whenever possible.

Andy