Hello everyone! Can anyone tell me or suggest a way to capture a RC servo PWM signal with a Xilinx CPLD in ABEL?. When the pulse duration is 1ms the digital value is logic 0, when is 2 ms the digital output is a logic 1. Best Regards Thanks in advance
RC Servo PWM Digital Capture in a Xilinx xc9500 CPLD?
Started by ●July 7, 2004
Reply by ●July 7, 20042004-07-07
Form the signal into a digital value. Use an external crystal or R/C oscillator to count the width of the pulse. A count of n in 1ms is a 0, a count of 2n is a 1. If all you need is a logical result and not a variable value, this threshold is pretty easy to program. "Bruno Cardeira" <bmscc@netcabo.pt> wrote in message news:40ec6b3b$0$508$a729d347@news.telepac.pt...> Hello everyone! > Can anyone tell me or suggest a way to capture a RC servo PWM signal witha> Xilinx CPLD in ABEL?. When the pulse duration is 1ms the digital value is > logic 0, when is 2 ms the digital output is a logic 1. > > Best Regards > Thanks in advance
Reply by ●July 7, 20042004-07-07
Bruno Cardeira wrote:> Hello everyone! > Can anyone tell me or suggest a way to capture a RC servo PWM signal with a > Xilinx CPLD in ABEL?. When the pulse duration is 1ms the digital value is > logic 0, when is 2 ms the digital output is a logic 1.In building block terms, this is a monostable and a D register. In a CPLD a monostable is built as an edge-reset-counter-compare. You could consider hysteresis on the time threshold, as the 1-2ms windows are usually linear. If it is multichannel RC, there is a frame signal to consider too. -jg
Reply by ●July 12, 20042004-07-12
thanks for the help john_H and Jim Granville! It's working! Bruno "Jim Granville" <no.spam@designtools.co.nz> escreveu na mensagem news:W_0Hc.6873$NA1.634567@news02.tsnz.net...> Bruno Cardeira wrote: > > Hello everyone! > > Can anyone tell me or suggest a way to capture a RC servo PWM signalwith a> > Xilinx CPLD in ABEL?. When the pulse duration is 1ms the digital valueis> > logic 0, when is 2 ms the digital output is a logic 1. > > In building block terms, this is a monostable and a D register. > In a CPLD a monostable is built as an edge-reset-counter-compare. > You could consider hysteresis on the time threshold, as the 1-2ms > windows are usually linear. > > If it is multichannel RC, there is a frame signal to consider too. > > -jg >