Spartan 3 termination question (DCI)

I'm looking at the DCI  (digitally controlled impedance) part of the
Spartan-3 spec, and I'm wondering if I can use this to eliminate the series
termination resistors on an IDE interface.  A typical IDE signal has a 22
ohm series resistor at the driver end and an 82 ohm series resistor at the
receiver end.  Typical bi-directional signals have a 33 ohm series resistor
at both ends.  If I understand the spec correctly, it looks like I can get
the series resistor at the driver end, but not at the receiver end.  Also on
the bi-di's I can get 33 ohms at each end, but the received signal would be
"picked off" before the 33 ohm resistor rather than after it...something you
could not do when the resistor was external.  So can I use any of this? or
do I need to stick to external termination?

Thanks
Dan

Dan,

Simulate it.

I doubt seriously that picking off the signal before or after a resistor 
at the receiver will make any difference at all (after all, the receiver 
has nearly infinite input impedance, and about 7-8 pF of capacitive 
loading, so what does a 82 ohm resistor to a 7 pF cap look like?  not 
much I assure you).

As for setting the DCI resistance, use 82 ohm, or 33 ohm reference 
resistors to set the DCI series drive impedance to 82 or 33 ohms.

I would simulate it in Hyperlynx using the various IBIS models fromt he 
different vendors to prove that it works with high and low Vcc, and with 
fast and slow process corners.

A standard is a starting point.  Either meet it exactly, and not worry, 
or simulate what you waht to do differently to prove it will always work 
the way you intend it to.

Your choice.  By the way, I even simulate a standard interface, as I do 
not trust that the standard's body could anticipate every possible use 
of their precious standard, or that every vendor really 'met' the 
standard when combined with the other vendors in the design.

Austin

Dan Kuechle wrote:
> I'm looking at the DCI  (digitally controlled impedance) part of the
> Spartan-3 spec, and I'm wondering if I can use this to eliminate the series
> termination resistors on an IDE interface.  A typical IDE signal has a 22
> ohm series resistor at the driver end and an 82 ohm series resistor at the
> receiver end.  Typical bi-directional signals have a 33 ohm series resistor
> at both ends.  If I understand the spec correctly, it looks like I can get
> the series resistor at the driver end, but not at the receiver end.  Also on
> the bi-di's I can get 33 ohms at each end, but the received signal would be
> "picked off" before the 33 ohm resistor rather than after it...something you
> could not do when the resistor was external.  So can I use any of this? or
> do I need to stick to external termination?
> 
> Thanks
> Dan
> 
> 

Dan, when you use series termination on a unidirectional line with one
driver and one receiver (the normal application), then you only
series-terminate the driver, and there should be no resistor at the
receiving end.
The idea is to match the driving end, send a half-amplitude signal down the
line, and make it bounce up to full strength at the unterminated receiver.
Series termination takes advantage of reflection, unstead of fighting it.
DCI is a nice way to manipulate the drive strength such that it matches the
line impedance.

Peter Alfke, Xilinx Applications

> From: "Dan Kuechle" <danielgk@voomtech.com>
> Organization: VISI.com
> Newsgroups: comp.arch.fpga
> Date: Fri, 9 Jul 2004 10:17:48 -0500
> Subject: Spartan 3 termination question (DCI)
> 
> I'm looking at the DCI  (digitally controlled impedance) part of the
> Spartan-3 spec, and I'm wondering if I can use this to eliminate the series
> termination resistors on an IDE interface.  A typical IDE signal has a 22
> ohm series resistor at the driver end and an 82 ohm series resistor at the
> receiver end.  Typical bi-directional signals have a 33 ohm series resistor
> at both ends.  If I understand the spec correctly, it looks like I can get
> the series resistor at the driver end, but not at the receiver end.  Also on
> the bi-di's I can get 33 ohms at each end, but the received signal would be
> "picked off" before the 33 ohm resistor rather than after it...something you
> could not do when the resistor was external.  So can I use any of this? or
> do I need to stick to external termination?
> 
> Thanks
> Dan
> 
> 

In article <BD1414E3.7665%peter@xilinx.com>,
 Peter Alfke <peter@xilinx.com> writes:
>Dan, when you use series termination on a unidirectional line with one
>driver and one receiver (the normal application), then you only
>series-terminate the driver, and there should be no resistor at the
>receiving end.
>The idea is to match the driving end, send a half-amplitude signal down the
>line, and make it bounce up to full strength at the unterminated receiver.
>Series termination takes advantage of reflection, unstead of fighting it.
>DCI is a nice way to manipulate the drive strength such that it matches the
>line impedance.

Also works for a bidirectional line if you put series resistors at both
ends.  The one at the receiver doesn't get in the way.  (At least not
much and/or at speeds where you are likely to be using bidirectional
lines.)

-- 
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other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
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On Fri, 09 Jul 2004 09:16:06 -0700, Austin Lesea wrote:

> Dan,
> 
> Simulate it.
> 
> I doubt seriously that picking off the signal before or after a resistor 
> at the receiver will make any difference at all (after all, the receiver 
> has nearly infinite input impedance, and about 7-8 pF of capacitive 
> loading, so what does a 82 ohm resistor to a 7 pF cap look like?  not 
> much I assure you).
> 
> As for setting the DCI resistance, use 82 ohm, or 33 ohm reference 
> resistors to set the DCI series drive impedance to 82 or 33 ohms.
> 
> I would simulate it in Hyperlynx using the various IBIS models fromt he 
> different vendors to prove that it works with high and low Vcc, and with 
> fast and slow process corners.
> 
> A standard is a starting point.  Either meet it exactly, and not worry, 
> or simulate what you waht to do differently to prove it will always work 
> the way you intend it to.
> 
> Your choice.  By the way, I even simulate a standard interface, as I do 
> not trust that the standard's body could anticipate every possible use 
> of their precious standard, or that every vendor really 'met' the 
> standard when combined with the other vendors in the design.
> 

Hyperlynx seemed like a good tool, but IIRC it didn't handle cables and
connectors very well.  

The best thing you can do on an ATA interface besides all the resistors
is to use the 80 conductor ultra-ATA cables. The extra return lines really
help.  Obviously keep the ATA cable as short as possible.  If you can only
put one device on the cable at the far end.  The ATA standard termination
scheme is really ad-hoc, it was never really addressed until the standard
started to push the speed envelope.

As for the DCI it does work, but my experience it's a real power hog.
We had a 64-bit DDR interface and turned it on for a trial, and what
used to be only a moderately warm FPGA turned into a burn-your-finger
cooker.

Andrew,

DCI series termination does not draw any significant power.  Only the 
parallel terminations are power hungry.  Just because the resitances are 
on chip rather than off chip does not mean that there is no power 
dissipated:  there is.  Same power as if the resistors where off chip.

Austin

Andrew Dyer wrote:
> On Fri, 09 Jul 2004 09:16:06 -0700, Austin Lesea wrote:
> 
> 
>>Dan,
>>
>>Simulate it.
>>
>>I doubt seriously that picking off the signal before or after a resistor 
>>at the receiver will make any difference at all (after all, the receiver 
>>has nearly infinite input impedance, and about 7-8 pF of capacitive 
>>loading, so what does a 82 ohm resistor to a 7 pF cap look like?  not 
>>much I assure you).
>>
>>As for setting the DCI resistance, use 82 ohm, or 33 ohm reference 
>>resistors to set the DCI series drive impedance to 82 or 33 ohms.
>>
>>I would simulate it in Hyperlynx using the various IBIS models fromt he 
>>different vendors to prove that it works with high and low Vcc, and with 
>>fast and slow process corners.
>>
>>A standard is a starting point.  Either meet it exactly, and not worry, 
>>or simulate what you waht to do differently to prove it will always work 
>>the way you intend it to.
>>
>>Your choice.  By the way, I even simulate a standard interface, as I do 
>>not trust that the standard's body could anticipate every possible use 
>>of their precious standard, or that every vendor really 'met' the 
>>standard when combined with the other vendors in the design.
>>
> 
> 
> Hyperlynx seemed like a good tool, but IIRC it didn't handle cables and
> connectors very well.  
> 
> The best thing you can do on an ATA interface besides all the resistors
> is to use the 80 conductor ultra-ATA cables. The extra return lines really
> help.  Obviously keep the ATA cable as short as possible.  If you can only
> put one device on the cable at the far end.  The ATA standard termination
> scheme is really ad-hoc, it was never really addressed until the standard
> started to push the speed envelope.
> 
> As for the DCI it does work, but my experience it's a real power hog.
> We had a 64-bit DDR interface and turned it on for a trial, and what
> used to be only a moderately warm FPGA turned into a burn-your-finger
> cooker.

Let's squash an urban legend:
In its normal use as series terminator, DCI shows insignificant additional
power dissipation ( and zero additional system power compared to external
resistors).
It is only when DCI is used as parallel termination that it draws a
continuous current and thus dissipates significant power.
Peter Alfke

> 
> As for the DCI it does work, but my experience it's a real power hog.
> We had a 64-bit DDR interface and turned it on for a trial, and what
> used to be only a moderately warm FPGA turned into a burn-your-finger
> cooker.

Peter wrote:
>
> In its normal use as series terminator, DCI shows insignificant additional
> power dissipation ( and zero additional system power compared to external
> resistors).
>
 A bit more than zero power is needed for Virtex 2 DCI when you
include the worst case VRP/VRN overhead power of ~200 mW/bank.

 Should be much better in V2Pro and S3 with the new DCI control
logic to cleanly stop the DCI updates.

Brian


Peter Alfke <peter@xilinx.com> wrote in message news:<BD18132B.76CC%peter@xilinx.com>...
> Let's squash an urban legend:
> In its normal use as series terminator, DCI shows insignificant additional
> power dissipation ( and zero additional system power compared to external
> resistors).
> It is only when DCI is used as parallel termination that it draws a
> continuous current and thus dissipates significant power.
> Peter Alfke
> 
> > 
> > As for the DCI it does work, but my experience it's a real power hog.
> > We had a 64-bit DDR interface and turned it on for a trial, and what
> > used to be only a moderately warm FPGA turned into a burn-your-finger
> > cooker.

Yesterday I wrote:
>
>  Should be much better in V2Pro and S3 with the new DCI
> control logic to cleanly stop the DCI updates.
>
 Or maybe not- according to the following Answer Record,
there's a 60 mA per bank hit when using LVDCI_33 in a 
Spartan 3, so the ~200 mW per bank number still applies.

 I'm not sure why it's still so high, as I thought the main
cause of the high overhead with the V2 DCI was that the
FreezeDCI option randomly stopped the DCI update logic at
whatever state it was in, possibly in an active R/2 matching
mode, rather than cleanly stopping it with VRP/VRN inactive.

Answer Record #19628 Spartan-3 - How does DCI affect power consumption? 

  "In an experiment performed to test current consumption when
    using LVDCI, Xilinx found that for every bank that turned
    on DCI, the device consumed an extra 60 mA of current"


Brian

Brian,

LVDCI_33 is 60 mA for the reference resistors.  For the whole bank.

Wow.  Sooooo much current!  Face it:  setting the reference for the 
entire bank does take some power (in this case 3.3V X 60 mA or 200 
milliwatts.  I am pretty sure this is not going to "break the bank."

Yes, and if you just had to have all 8 banks use DCI, that would be 8 
times as much current.  I suggest that you confine the DCI interfaces to 
those banks that need them, not just for the 200 milliwatts.

Freeze DCI has nothing to do with it.  The DCI circuit has to solve for 
1/2 R, R and 2R, so the average current consumption is higher than it 
would be for R alone.

One trick you can use to cut it in half is to use 100 ohm reference 
resistors, and use LVDCI_DV2 (divide by two) to get 50 ohm drive.

Now you have 100 milliwatts dissipated for the feature of using DCI  in 
the bank.

If you are thinking "why did they not use 10X reference resistors? (to 
lower power per bank)" the answer is very simple:  the noise in a 
typical system would trash a higher impedance reference system, and the 
feature would have to be abandoned (or fixed)  -- sound familiar?.  From 
the first appearance of DCI in Virtex II, it has been a solid feature in 
every device since.

DCI updating is only an issue when you cross between two banks, and even 
then only with the parallel interfaces where it adds some small amount 
of jitter.  Freezing the updates allowed customers who did not read that 
they should not go across banks to modify the bitstream, rather than 
re-design their pcbs.  It also allowed the highest speed interfaces to 
have more timing margin (budget) which makes memory interfacing easier.

It is always preferable to provide the customer with solutions that 
involve changing bits, rather than making new boards (and them failing 
to place the orders that we desire).  Now we have three different DCI 
options:  regular (runs all the time changing +/- one trim), changes 
only when reguired, and "frozen" after matching (at configuration time).

Austin

Brian Davis wrote:
> Yesterday I wrote:
> 
>> Should be much better in V2Pro and S3 with the new DCI
>>control logic to cleanly stop the DCI updates.
>>
> 
>  Or maybe not- according to the following Answer Record,
> there's a 60 mA per bank hit when using LVDCI_33 in a 
> Spartan 3, so the ~200 mW per bank number still applies.
> 
>  I'm not sure why it's still so high, as I thought the main
> cause of the high overhead with the V2 DCI was that the
> FreezeDCI option randomly stopped the DCI update logic at
> whatever state it was in, possibly in an active R/2 matching
> mode, rather than cleanly stopping it with VRP/VRN inactive.
> 
> Answer Record #19628 Spartan-3 - How does DCI affect power consumption? 
> 
>   "In an experiment performed to test current consumption when
>     using LVDCI, Xilinx found that for every bank that turned
>     on DCI, the device consumed an extra 60 mA of current"
> 
> 
> Brian