New to FPGA, seeking advice

Hi

I'm an embedded systems designer who feels that it's about time he
started to learn about using FPGAs. I'm happy using PLDs, designed in
something like CUPL but don't know where to start on bigger devices.

I only have a small budget for development tools and I'm in the UK.

From what I can see my best choice of manufacturer is probably down to
Xilinx or Altera.

Can anyone suggest an evaluation board that would get me started?

I see that devices are sold in terms of their gate count. How
efficient is a typical design? For instance, if I want to make a 16 by
16 CPU controlled crosspoint how many FPGA gates will I need? I can
see that I need 16 OR gates each with 16 AND array inputs for the
output terms, 64 latches to store the selection and some more gates to
do the latch address decoding. Is there any easy way to choose the
right part?

Thanks

Brian
-- 
Brian Fairchild
B dot Fairchild at Dial dot Pipex dot Com

"But apart from that Mrs Lincoln, how did you enjoy the play?"

Hello Brian,

Take a look at these:
http://www.digilentinc.com/Catalog/digilab_2e.html
http://www.digilentinc.com/Catalog/peripheral_boards.html

To start experimenting you'll need a System Board and one of the 
peripheral boards.
The Spartan2e on this board has 200K gates, for your design it should be 
way too big... to give you an idea of what you can get into it, take a 
look at the list of applications they give at the Xilinx ip center.

Good luck

Yves

Brian Fairchild wrote:
> Hi
> 
> I'm an embedded systems designer who feels that it's about time he
> started to learn about using FPGAs. I'm happy using PLDs, designed in
> something like CUPL but don't know where to start on bigger devices.
> 
> I only have a small budget for development tools and I'm in the UK.
> 
> From what I can see my best choice of manufacturer is probably down to
> Xilinx or Altera.
> 
> Can anyone suggest an evaluation board that would get me started?
> 
> I see that devices are sold in terms of their gate count. How
> efficient is a typical design? For instance, if I want to make a 16 by
> 16 CPU controlled crosspoint how many FPGA gates will I need? I can
> see that I need 16 OR gates each with 16 AND array inputs for the
> output terms, 64 latches to store the selection and some more gates to
> do the latch address decoding. Is there any easy way to choose the
> right part?
> 
> Thanks
> 
> Brian
> 

Brian Fairchild wrote:

Hi Brian,

> I'm an embedded systems designer who feels that it's about time he
> started to learn about using FPGAs. I'm happy using PLDs, designed in
> something like CUPL but don't know where to start on bigger devices.
> 
> I only have a small budget for development tools and I'm in the UK.
> 
> From what I can see my best choice of manufacturer is probably down to
> Xilinx or Altera.
> 
> Can anyone suggest an evaluation board that would get me started?

You might have a look at http://www.silica.com/eval_kits/index.html
There are some good evaluation boards that are not so expensive.

> I see that devices are sold in terms of their gate count. How
> efficient is a typical design? For instance, if I want to make a 16 by
> 16 CPU controlled crosspoint how many FPGA gates will I need? I can
> see that I need 16 OR gates each with 16 AND array inputs for the
> output terms, 64 latches to store the selection and some more gates to
> do the latch address decoding. Is there any easy way to choose the
> right part?

That is very difficult to answer. This issue has been discussed sometimes 
in this newsgroup already, and will probably be discussed again and again.

You should never ever draw some conclusions from the gate-count
given by the manufacturers. This is just a marketing number.
I started with Lucent (now Lattice) ORCA FPGAs and got a feeling 
what can be put inside. Then I turned to Xilinx Virtex FPGAs (because 
of the free development software) and got rather shocked how much 
less one can put into such an FPGA with a comparable gate count. 

For instance, they include internal RAM-Blocks in the official 
gate-count number. That gives a shiny value, but is nonsense if 
you ask me.
My guess is that the Xilinx people that are around here in this 
newsgroup think similar because they are more engineers rather than
marketing people.
But apart from that, the Xilinx FPGAs are not bad ones.

Instead, have a look at the building blocks, see what they provide
and how much of them are available and then draw conclusions whether 
it is sufficient for your design. And when you made some designs for 
a specific FPGA series, you will soon develop a feeling which 
array size could be appropriate for which problem. 

Once you got some design software, you might also try to synthesize 
your design (provided it has been finished already) and try to fit 
it into different FPGA types. There you will also see how much of 
the FPGAs' capacity would be used.

Regards,
Mario  

"Mario Trams" <Mario.Trams@informatik.tu-chemnitz.de> wrote in message
news:bj70hb$3j3$1@anderson.hrz.tu-chemnitz.de...

(snip)

> > I see that devices are sold in terms of their gate count. How
> > efficient is a typical design? For instance, if I want to make a 16 by
> > 16 CPU controlled crosspoint how many FPGA gates will I need? I can
> > see that I need 16 OR gates each with 16 AND array inputs for the
> > output terms, 64 latches to store the selection and some more gates to
> > do the latch address decoding. Is there any easy way to choose the
> > right part?
>
> That is very difficult to answer. This issue has been discussed sometimes
> in this newsgroup already, and will probably be discussed again and again.
>
> You should never ever draw some conclusions from the gate-count
> given by the manufacturers. This is just a marketing number.
> I started with Lucent (now Lattice) ORCA FPGAs and got a feeling
> what can be put inside. Then I turned to Xilinx Virtex FPGAs (because
> of the free development software) and got rather shocked how much
> less one can put into such an FPGA with a comparable gate count.

Well, some designs fit the FPGA model better than others.   My guess is that
a crossbar switch is one that doesn't fit very well, but that is a guess.

> For instance, they include internal RAM-Blocks in the official
> gate-count number. That gives a shiny value, but is nonsense if
> you ask me.
> My guess is that the Xilinx people that are around here in this
> newsgroup think similar because they are more engineers rather than
> marketing people.
> But apart from that, the Xilinx FPGAs are not bad ones.

The traditional CMOS definition for gate count is the number of transistors
divided by four.  It takes four to make a CMOS 2 input NAND gate.  RAM
arrays are included in that count.

(snip)

> Once you got some design software, you might also try to synthesize
> your design (provided it has been finished already) and try to fit
> it into different FPGA types. There you will also see how much of
> the FPGAs' capacity would be used.

This is probably the best way.  First, the manufacturer given gate count is
a maximum, and you should expect somewhat less.   There may be a wide
variation on how much you actually get.


-- glen

All,

I beg to differ.  We have not only a good solution, but a great solution:

http://www.xilinx.com/prs_rls/end_markets/02151crossbar.htm

The worlds first FPGA cross bar switch that uses the programmable interconnect
as....well, as a corss bar switch!  Extremely efficient (able to do 1024x1024 in
a 2V6000 at 155 Mbs each wire, non-blocking).

For a really small cross bar, one could use the ICAP with the microblaze for
control, and a bram for the patterns....and perhaps only 16 CLBs for a 16X16
non-blocking cross point switch.....

Austin

Glen Herrmannsfeldt wrote:

> "Mario Trams" <Mario.Trams@informatik.tu-chemnitz.de> wrote in message
> news:bj70hb$3j3$1@anderson.hrz.tu-chemnitz.de...
>
> (snip)
>
> > > I see that devices are sold in terms of their gate count. How
> > > efficient is a typical design? For instance, if I want to make a 16 by
> > > 16 CPU controlled crosspoint how many FPGA gates will I need? I can
> > > see that I need 16 OR gates each with 16 AND array inputs for the
> > > output terms, 64 latches to store the selection and some more gates to
> > > do the latch address decoding. Is there any easy way to choose the
> > > right part?
> >
> > That is very difficult to answer. This issue has been discussed sometimes
> > in this newsgroup already, and will probably be discussed again and again.
> >
> > You should never ever draw some conclusions from the gate-count
> > given by the manufacturers. This is just a marketing number.
> > I started with Lucent (now Lattice) ORCA FPGAs and got a feeling
> > what can be put inside. Then I turned to Xilinx Virtex FPGAs (because
> > of the free development software) and got rather shocked how much
> > less one can put into such an FPGA with a comparable gate count.
>
> Well, some designs fit the FPGA model better than others.   My guess is that
> a crossbar switch is one that doesn't fit very well, but that is a guess.
>
> > For instance, they include internal RAM-Blocks in the official
> > gate-count number. That gives a shiny value, but is nonsense if
> > you ask me.
> > My guess is that the Xilinx people that are around here in this
> > newsgroup think similar because they are more engineers rather than
> > marketing people.
> > But apart from that, the Xilinx FPGAs are not bad ones.
>
> The traditional CMOS definition for gate count is the number of transistors
> divided by four.  It takes four to make a CMOS 2 input NAND gate.  RAM
> arrays are included in that count.
>
> (snip)
>
> > Once you got some design software, you might also try to synthesize
> > your design (provided it has been finished already) and try to fit
> > it into different FPGA types. There you will also see how much of
> > the FPGAs' capacity would be used.
>
> This is probably the best way.  First, the manufacturer given gate count is
> a maximum, and you should expect somewhat less.   There may be a wide
> variation on how much you actually get.
>
> -- glen

"Brian Fairchild" <spam.spam@spam.com> wrote in message
news:jhcclv0p5n1628t9s1cdfpthac60ltjub4@4ax.com...

> efficient is a typical design? For instance, if I want to make a 16 by
> 16 CPU controlled crosspoint how many FPGA gates will I need? I can
> see that I need 16 OR gates each with 16 AND array inputs for the
> output terms, 64 latches to store the selection and some more gates to
> do the latch address decoding. Is there any easy way to choose the

Just as an academic thing for myself.

Is a bi-directional crosspoint switch able to be produced with a FPGA?  My
understanding is they are a matrix of fets each one having a memory cell to
store it's setting.

So I would say that it was impossible. Even a fully digital one would still
require that an an I/O pin can be used for input and output at the same
time.

Can anyone confirm or deny?

Thanks
Ralph

In a flurry of electrons Ralph Mason spake thus:

>"Brian Fairchild" <spam.spam@spam.com> wrote in message
>news:jhcclv0p5n1628t9s1cdfpthac60ltjub4@4ax.com...
>
>> efficient is a typical design? For instance, if I want to make a 16 by
>> 16 CPU controlled crosspoint how many FPGA gates will I need? I can
>> see that I need 16 OR gates each with 16 AND array inputs for the
>> output terms, 64 latches to store the selection and some more gates to
>> do the latch address decoding. Is there any easy way to choose the
>
>Just as an academic thing for myself.
>
>Is a bi-directional crosspoint switch able to be produced with a FPGA?  My
>understanding is they are a matrix of fets each one having a memory cell to
>store it's setting.
>
>So I would say that it was impossible. Even a fully digital one would still
>require that an an I/O pin can be used for input and output at the same
>time.

To clarify, what I wanted to do as an example was a uni-directional
crosspoint.
-- 
Brian Fairchild
B dot Fairchild at Dial dot Pipex dot Com

"But apart from that Mrs Lincoln, how did you enjoy the play?"

"Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message
news:3F5782D1.746E1D51@xilinx.com...
> All,
>
> I beg to differ.  We have not only a good solution, but a great solution:
>
> http://www.xilinx.com/prs_rls/end_markets/02151crossbar.htm
>
> The worlds first FPGA cross bar switch that uses the programmable
interconnect
> as....well, as a corss bar switch!  Extremely efficient (able to do
1024x1024 in
> a 2V6000 at 155 Mbs each wire, non-blocking).
>
> For a really small cross bar, one could use the ICAP with the microblaze
for
> control, and a bram for the patterns....and perhaps only 16 CLBs for a
16X16
> non-blocking cross point switch.....

That does sound pretty neat.   I was thinking of it in terms of
synthesizable logic using CLB's.

Can you do a barrel shifter for floating point
prenormalization/postnormalization that way, too?

-- glen

Actually, the xilinx structure can make a very efficient cross bar.  One way is
to do a partial reconfiguration to switch the crossbar connections, in which
case it uses mostly just the routing resources, not CLBs.  If partial
reconfiguration is not your cup of tea, you can make efficient 4:1 muxes using
SRL16's. These take 16 clocks to reroute, and require a simple loader which can
be shared among many bits, but they are compact and fast.

Glen Herrmannsfeldt wrote:

> "Mario Trams" <Mario.Trams@informatik.tu-chemnitz.de> wrote in message
> news:bj70hb$3j3$1@anderson.hrz.tu-chemnitz.de...
>
> (snip)
>
> > > I see that devices are sold in terms of their gate count. How
> > > efficient is a typical design? For instance, if I want to make a 16 by
> > > 16 CPU controlled crosspoint how many FPGA gates will I need? I can
> > > see that I need 16 OR gates each with 16 AND array inputs for the
> > > output terms, 64 latches to store the selection and some more gates to
> > > do the latch address decoding. Is there any easy way to choose the
> > > right part?
> >
> > That is very difficult to answer. This issue has been discussed sometimes
> > in this newsgroup already, and will probably be discussed again and again.
> >
> > You should never ever draw some conclusions from the gate-count
> > given by the manufacturers. This is just a marketing number.
> > I started with Lucent (now Lattice) ORCA FPGAs and got a feeling
> > what can be put inside. Then I turned to Xilinx Virtex FPGAs (because
> > of the free development software) and got rather shocked how much
> > less one can put into such an FPGA with a comparable gate count.
>
> Well, some designs fit the FPGA model better than others.   My guess is that
> a crossbar switch is one that doesn't fit very well, but that is a guess.
>
> > For instance, they include internal RAM-Blocks in the official
> > gate-count number. That gives a shiny value, but is nonsense if
> > you ask me.
> > My guess is that the Xilinx people that are around here in this
> > newsgroup think similar because they are more engineers rather than
> > marketing people.
> > But apart from that, the Xilinx FPGAs are not bad ones.
>
> The traditional CMOS definition for gate count is the number of transistors
> divided by four.  It takes four to make a CMOS 2 input NAND gate.  RAM
> arrays are included in that count.
>
> (snip)
>
> > Once you got some design software, you might also try to synthesize
> > your design (provided it has been finished already) and try to fit
> > it into different FPGA types. There you will also see how much of
> > the FPGAs' capacity would be used.
>
> This is probably the best way.  First, the manufacturer given gate count is
> a maximum, and you should expect somewhat less.   There may be a wide
> variation on how much you actually get.
>
> -- glen

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

Glen,

Do not see why not.  The downside is that you need to reconfigure the
interconnect to change a cross point, so the update rate is slow.  For most
traffic bearing circuit switch applications, a few ms to change the x-point is
not an issue, but for a packet system it would not be fast enough.

A barrel shifter seems like something you would want to update very quickly,
and for that, you would probably rather use the multiplier as a barrel shifter.

Austin

Glen Herrmannsfeldt wrote:

> "Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message
> news:3F5782D1.746E1D51@xilinx.com...
> > All,
> >
> > I beg to differ.  We have not only a good solution, but a great solution:
> >
> > http://www.xilinx.com/prs_rls/end_markets/02151crossbar.htm
> >
> > The worlds first FPGA cross bar switch that uses the programmable
> interconnect
> > as....well, as a corss bar switch!  Extremely efficient (able to do
> 1024x1024 in
> > a 2V6000 at 155 Mbs each wire, non-blocking).
> >
> > For a really small cross bar, one could use the ICAP with the microblaze
> for
> > control, and a bram for the patterns....and perhaps only 16 CLBs for a
> 16X16
> > non-blocking cross point switch.....
>
> That does sound pretty neat.   I was thinking of it in terms of
> synthesizable logic using CLB's.
>
> Can you do a barrel shifter for floating point
> prenormalization/postnormalization that way, too?
>
> -- glen