Due to a chip bug, I have to extend a pulse width(negative)from 10ns to 100ms in CPLD(Altera 7128). But the difficult is that I have no any clock into the CPLD, so the CPLD is pure combination logic. how to extend it in such case? Help me!
How to extend a pulse width without clock in CPLD!
Started by ●September 4, 2003