Hello I'd like to know if anybody had any success in using Xilinx OPB/PCI bridge core using EDK. I set up the project and configured all the core parameters correctly. I also double checked the constraint file for pin assignments for the PCI finger. The compile and programming process goes well without any error, but I cannot even get my host PC to recognize my development board with the PCI bitmap. I am using Avnet's Virtex II PCI Development Board. Thanks for your input in advance.
Xilinx EDK PCI
Started by ●July 15, 2004
Reply by ●July 16, 20042004-07-16
Reply by ●July 16, 20042004-07-16
This is a multi-part message in MIME format. ------=_NextPart_000_001B_01C46B40.DC30A130 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Joe Avnet does not make host drivers. Either way it should still show up on = the Device Manager in Windows or lspci in Linux as an undefined device = if the configuration cycles of the PCI core are working correctly. I = tried to find this out with a logic analyzer but no luck. Thanks for you = help though. -Jackson <joe> wrote in message news:ee878f6.0@webx.sUN8CHnE... Have you installed a PCI driver for the board on the host PC? What Os = are you using? ------=_NextPart_000_001B_01C46B40.DC30A130 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD> <META http-equiv=3DContent-Type content=3D"text/html; = charset=3Diso-8859-1"> <META content=3D"MSHTML 6.00.2800.1400" name=3DGENERATOR> <STYLE></STYLE> </HEAD> <BODY bgColor=3D#ffffff> <DIV><FONT face=3DArial size=3D2>Joe</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2>Avnet does not make host drivers. = Either way it=20 should still show up on the Device Manager in Windows or lspci in Linux = as an=20 undefined device if the configuration cycles of the PCI core are = working=20 correctly. I tried to find this out with a logic analyzer but no = luck.=20 Thanks for you help though.</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2>-Jackson</FONT></DIV> <BLOCKQUOTE=20 style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; = BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px"> <DIV><joe> wrote in message <A=20 = href=3D"news:ee878f6.0@webx.sUN8CHnE">news:ee878f6.0@webx.sUN8CHnE</A>...= </DIV>Have=20 you installed a PCI driver for the board on the host PC? What Os are = you=20 using?</BLOCKQUOTE></BODY></HTML> ------=_NextPart_000_001B_01C46B40.DC30A130--
Reply by ●July 19, 20042004-07-19
Reply by ●July 26, 20042004-07-26
This is a multi-part message in MIME format. ------=_NextPart_000_001F_01C47311.056DD9A0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hi Seb I used EDK 6.2 Here's the .mhs PARAMETER VERSION =3D 2.1.0 PORT clk_40mhz =3D clk_40mhz, DIR =3D I, SIGIS =3D CLK PORT pci_TRDY_N =3D pci_TRDY_N, DIR =3D IO PORT pci_CBE =3D pci_CBE, VEC =3D [0:3], DIR =3D IO PORT pci_DEVSEL_N =3D pci_DEVSEL_N, DIR =3D IO PORT pci_FRAME_N =3D pci_FRAME_N, DIR =3D IO PORT pci_AD =3D pci_AD, VEC =3D [0:31], DIR =3D IO PORT pci_SERR_N =3D pci_SERR_N, DIR =3D IO PORT pci_IDSEL =3D pci_IDSEL, DIR =3D I PORT pci_INTR_A =3D pci_INTR_A, DIR =3D O PORT pci_IRDY_N =3D pci_IRDY_N, DIR =3D IO PORT pci_PAR =3D pci_PAR, DIR =3D IO PORT pci_GNT_N =3D pci_GNT_N, DIR =3D I PORT pci_Freeze =3D pci_Freeze, DIR =3D I PORT pci_PCLK =3D pci_PCLK, DIR =3D I PORT pci_STOP_N =3D pci_STOP_N, DIR =3D IO PORT pci_RST_N =3D pci_RST_N, DIR =3D I PORT pci_REQ_N =3D pci_REQ_N, DIR =3D O PORT pci_PERR_N =3D pci_PERR_N, DIR =3D IO PORT RS232_RX =3D RS232_RX, DIR =3D I PORT RS232_TX =3D RS232_TX, DIR =3D O PORT led_pin =3D led_pin, VEC =3D [0:7], DIR =3D IO PORT sw_pin =3D sw_pin, VEC =3D [0:7], DIR =3D IO PORT sys_clk =3D sys_clk, DIR =3D I, SIGIS =3D Clk PORT sys_rst =3D sys_rst, DIR =3D I BEGIN microblaze PARAMETER INSTANCE =3D mblaze PARAMETER HW_VER =3D 2.00.a BUS_INTERFACE DLMB =3D d_lmb BUS_INTERFACE ILMB =3D i_lmb BUS_INTERFACE DOPB =3D d_opb BUS_INTERFACE IOPB =3D d_opb PORT CLK =3D clk_40mhz PORT INTERRUPT =3D mblaze_int END BEGIN bram_block PARAMETER INSTANCE =3D bram PARAMETER HW_VER =3D 1.00.a BUS_INTERFACE PORTA =3D data BUS_INTERFACE PORTB =3D inst END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE =3D i_bram_cntrl PARAMETER HW_VER =3D 1.00.b PARAMETER C_BASEADDR =3D 0x00000000 PARAMETER C_HIGHADDR =3D 0x00007FFF BUS_INTERFACE SLMB =3D i_lmb BUS_INTERFACE BRAM_PORT =3D data PORT LMB_Clk =3D clk_40mhz END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE =3D d_bram_cntrl PARAMETER HW_VER =3D 1.00.b PARAMETER C_BASEADDR =3D 0x00000000 PARAMETER C_HIGHADDR =3D 0x00007FFF BUS_INTERFACE SLMB =3D d_lmb BUS_INTERFACE BRAM_PORT =3D inst PORT LMB_Clk =3D clk_40mhz END BEGIN opb_pci PARAMETER INSTANCE =3D pci PARAMETER HW_VER =3D 1.00.b PARAMETER C_BASEADDR =3D 0x00009000 PARAMETER C_HIGHADDR =3D 0x00009FFF PARAMETER C_PCIBAR_NUM =3D 2 PARAMETER C_PCIBAR_LEN_0 =3D 15 PARAMETER C_PCIBAR2IPIF_0 =3D 0x00008000 PARAMETER C_PCIBAR_ENDIAN_TRANSLATE_EN_0 =3D 1 PARAMETER C_PCI_PREFETCH_0 =3D 1 PARAMETER C_PCI_SPACETYPE_0 =3D 1 PARAMETER C_IPIFBAR_NUM =3D 1 PARAMETER C_IPIF_HIGHADDR_0 =3D 0x0000FFFF PARAMETER C_IPIFBAR2PCI_0 =3D 0x0 PARAMETER C_IPIFBAR_ENDIAN_TRANSLATE_EN_0 =3D 1 PARAMETER C_IPIF_PREFETCH_0 =3D 1 PARAMETER C_IPIF_SPACETYPE_0 =3D 1 PARAMETER C_NUM_INTERRUPTS =3D 13 PARAMETER C_OPB_CLK_PERIOD_PS =3D 25000 PARAMETER C_CLASS_CODE =3D 0x028000 PARAMETER C_DEVICE_ID =3D 0x9050 PARAMETER C_DMA_HIGHADDR =3D 0x0000A77F PARAMETER C_DMA_CHAN_TYPE =3D 0 PARAMETER C_DMA_LENGTH_WIDTH =3D 15 PARAMETER C_DEV_MIR_ENABLE =3D 1 PARAMETER C_INCLUDE_DEV_ISC =3D 1 PARAMETER C_IPIFBAR_1 =3D 0x0000A600 PARAMETER C_IPIF_HIGHADDR_1 =3D 0x0000A61F PARAMETER C_IPIFBAR2PCI_1 =3D 0x0 PARAMETER C_IPIFBAR_ENDIAN_TRANSLATE_EN_1 =3D 1 PARAMETER C_IPIF_PREFETCH_1 =3D 1 PARAMETER C_IPIF_SPACETYPE_1 =3D 1 PARAMETER C_PCIBAR_1 =3D 0xFFFFFFF8 PARAMETER C_PCIBAR_LEN_1 =3D 4 PARAMETER C_PCIBAR2IPIF_1 =3D 0x0000A600 PARAMETER C_PCIBAR_ENDIAN_TRANSLATE_EN_1 =3D 1 PARAMETER C_PCI_PREFETCH_1 =3D 1 PARAMETER C_PCI_SPACETYPE_1 =3D 1 PARAMETER C_VENDOR_ID =3D 0x10B7 PARAMETER C_INCLUDE_PCI_CONFIG =3D 1 PARAMETER C_REV_ID =3D 0x01 PARAMETER C_MAX_LAT =3D 0x08 PARAMETER C_MIN_GNT =3D 0x03 PARAMETER C_NUM_IDSEL =3D 1 PARAMETER C_DMA_BASEADDR =3D 0x0000A700 PARAMETER C_PCIBAR_0 =3D 0xFFFF0008 PARAMETER C_IPIFBAR_0 =3D 0x00008000 BUS_INTERFACE MSOPB =3D d_opb PORT TRDY_N =3D pci_TRDY_N PORT OPB_Clk =3D clk_40mhz PORT CBE =3D pci_CBE PORT DEVSEL_N =3D pci_DEVSEL_N PORT FRAME_N =3D pci_FRAME_N PORT AD =3D pci_AD PORT SERR_N =3D pci_SERR_N PORT IDSEL =3D pci_IDSEL PORT INTR_A =3D pci_INTR_A PORT IRDY_N =3D pci_IRDY_N PORT PAR =3D pci_PAR PORT GNT_N =3D pci_GNT_N PORT Freeze =3D pci_Freeze PORT PCLK =3D pci_PCLK PORT STOP_N =3D pci_STOP_N PORT RST_N =3D pci_RST_N PORT REQ_N =3D pci_REQ_N PORT PERR_N =3D pci_PERR_N END BEGIN opb_uartlite PARAMETER INSTANCE =3D uart PARAMETER HW_VER =3D 1.00.b PARAMETER C_BASEADDR =3D 0x0000A000 PARAMETER C_HIGHADDR =3D 0x0000A0FF PARAMETER C_DATA_BITS =3D 8 PARAMETER C_CLK_FREQ =3D 40000000 PARAMETER C_BAUDRATE =3D 9600 PARAMETER C_USE_PARITY =3D 0 PARAMETER C_ODD_PARITY =3D 0 BUS_INTERFACE SOPB =3D d_opb PORT OPB_Clk =3D clk_40mhz PORT RX =3D RS232_RX PORT TX =3D RS232_TX PORT Interrupt =3D net_gnd END BEGIN opb_jtag_uart PARAMETER INSTANCE =3D jtag_uart PARAMETER HW_VER =3D 1.00.b PARAMETER C_BASEADDR =3D 0x0000A100 PARAMETER C_HIGHADDR =3D 0x0000A1FF BUS_INTERFACE SOPB =3D d_opb PORT Interrupt =3D net_gnd PORT OPB_Clk =3D clk_40mhz END BEGIN lmb_v10 PARAMETER INSTANCE =3D d_lmb PARAMETER HW_VER =3D 1.00.a PORT SYS_Rst =3D sys_rst PORT LMB_Clk =3D clk_40mhz END BEGIN lmb_v10 PARAMETER INSTANCE =3D i_lmb PARAMETER HW_VER =3D 1.00.a PORT SYS_Rst =3D sys_rst PORT LMB_Clk =3D clk_40mhz END BEGIN opb_v20 PARAMETER INSTANCE =3D d_opb PARAMETER HW_VER =3D 1.10.b PARAMETER C_BASEADDR =3D 0xFF020000 PARAMETER C_HIGHADDR =3D 0xFF0201FF PARAMETER C_PROC_INTRFCE =3D 1 PORT SYS_Rst =3D sys_rst PORT OPB_Clk =3D clk_40mhz END BEGIN opb_gpio PARAMETER INSTANCE =3D led PARAMETER HW_VER =3D 2.00.a PARAMETER C_BASEADDR =3D 0x0000A200 PARAMETER C_HIGHADDR =3D 0x0000A2FF PARAMETER C_GPIO_WIDTH =3D 8 BUS_INTERFACE SOPB =3D d_opb PORT OPB_Clk =3D clk_40mhz PORT GPIO_IO =3D led_pin END BEGIN opb_gpio PARAMETER INSTANCE =3D sw PARAMETER HW_VER =3D 2.00.a PARAMETER C_BASEADDR =3D 0x0000A300 PARAMETER C_HIGHADDR =3D 0x0000A3FF PARAMETER C_GPIO_WIDTH =3D 8 BUS_INTERFACE SOPB =3D d_opb PORT GPIO_IO =3D sw_pin PORT OPB_Clk =3D clk_40mhz END BEGIN opb_intc PARAMETER INSTANCE =3D intc PARAMETER HW_VER =3D 1.00.c PARAMETER C_BASEADDR =3D 0x0000A400 PARAMETER C_HIGHADDR =3D 0x0000A4FF PARAMETER C_IRQ_IS_LEVEL =3D 0 BUS_INTERFACE SOPB =3D d_opb PORT OPB_Clk =3D clk_40mhz PORT Intr =3D bar_int_Intr PORT Irq =3D mblaze_int END BEGIN opb_interrupt_generator PARAMETER INSTANCE =3D bar_int PARAMETER C_BASEADDR =3D 0x0000A600 PARAMETER C_HIGHADDR =3D 0x0000A60F BUS_INTERFACE SOPB =3D d_opb PORT opb_clk =3D sys_clk PORT Interrupt =3D bar_int_Intr END BEGIN opb_bram_if_cntlr PARAMETER INSTANCE =3D pk_mem PARAMETER HW_VER =3D 1.00.a PARAMETER C_BASEADDR =3D 0x00008000 PARAMETER C_HIGHADDR =3D 0x0000FFFF END "seb" <sebastien.longueville@fr.thalesgroup.com> wrote in message = news:ee878f6.2@webx.sUN8CHnE... Which EDK version do you use ?=20 Could you paste your MHS file ? ------=_NextPart_000_001F_01C47311.056DD9A0 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD> <META http-equiv=3DContent-Type content=3D"text/html; = charset=3Diso-8859-1"> <META content=3D"MSHTML 6.00.2800.1400" name=3DGENERATOR> <STYLE></STYLE> </HEAD> <BODY bgColor=3D#ffffff> <DIV><FONT face=3DArial size=3D2>Hi Seb</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2>I used EDK 6.2</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2>Here's the .mhs</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV> </DIV> <DIV><FONT face=3DArial size=3D2> PARAMETER VERSION =3D = 2.1.0</FONT></DIV> <DIV> </DIV><FONT face=3DArial size=3D2> <DIV><BR> PORT clk_40mhz =3D clk_40mhz, DIR =3D I, SIGIS =3D = CLK<BR> PORT=20 pci_TRDY_N =3D pci_TRDY_N, DIR =3D IO<BR> PORT pci_CBE =3D pci_CBE, = VEC =3D [0:3],=20 DIR =3D IO<BR> PORT pci_DEVSEL_N =3D pci_DEVSEL_N, DIR =3D = IO<BR> PORT=20 pci_FRAME_N =3D pci_FRAME_N, DIR =3D IO<BR> PORT pci_AD =3D pci_AD, = VEC =3D [0:31],=20 DIR =3D IO<BR> PORT pci_SERR_N =3D pci_SERR_N, DIR =3D = IO<BR> PORT pci_IDSEL=20 =3D pci_IDSEL, DIR =3D I<BR> PORT pci_INTR_A =3D pci_INTR_A, DIR = =3D=20 O<BR> PORT pci_IRDY_N =3D pci_IRDY_N, DIR =3D IO<BR> PORT = pci_PAR =3D=20 pci_PAR, DIR =3D IO<BR> PORT pci_GNT_N =3D pci_GNT_N, DIR =3D = I<BR> PORT=20 pci_Freeze =3D pci_Freeze, DIR =3D I<BR> PORT pci_PCLK =3D = pci_PCLK, DIR =3D=20 I<BR> PORT pci_STOP_N =3D pci_STOP_N, DIR =3D IO<BR> PORT = pci_RST_N =3D=20 pci_RST_N, DIR =3D I<BR> PORT pci_REQ_N =3D pci_REQ_N, DIR =3D = O<BR> PORT=20 pci_PERR_N =3D pci_PERR_N, DIR =3D IO<BR> PORT RS232_RX =3D = RS232_RX, DIR =3D=20 I<BR> PORT RS232_TX =3D RS232_TX, DIR =3D O<BR> PORT led_pin = =3D led_pin,=20 VEC =3D [0:7], DIR =3D IO<BR> PORT sw_pin =3D sw_pin, VEC =3D = [0:7], DIR =3D=20 IO<BR> PORT sys_clk =3D sys_clk, DIR =3D I, SIGIS =3D = Clk<BR> PORT sys_rst =3D=20 sys_rst, DIR =3D I</DIV> <DIV> </DIV> <DIV><BR>BEGIN microblaze<BR> PARAMETER INSTANCE =3D=20 mblaze<BR> PARAMETER HW_VER =3D 2.00.a<BR> BUS_INTERFACE DLMB = =3D=20 d_lmb<BR> BUS_INTERFACE ILMB =3D i_lmb<BR> BUS_INTERFACE DOPB = =3D=20 d_opb<BR> BUS_INTERFACE IOPB =3D d_opb<BR> PORT CLK =3D=20 clk_40mhz<BR> PORT INTERRUPT =3D mblaze_int<BR>END</DIV> <DIV> </DIV> <DIV>BEGIN bram_block<BR> PARAMETER INSTANCE =3D = bram<BR> PARAMETER=20 HW_VER =3D 1.00.a<BR> BUS_INTERFACE PORTA =3D = data<BR> BUS_INTERFACE PORTB=20 =3D inst<BR>END</DIV> <DIV> </DIV> <DIV>BEGIN lmb_bram_if_cntlr<BR> PARAMETER INSTANCE =3D=20 i_bram_cntrl<BR> PARAMETER HW_VER =3D 1.00.b<BR> PARAMETER = C_BASEADDR =3D=20 0x00000000<BR> PARAMETER C_HIGHADDR =3D = 0x00007FFF<BR> BUS_INTERFACE=20 SLMB =3D i_lmb<BR> BUS_INTERFACE BRAM_PORT =3D data<BR> PORT = LMB_Clk =3D=20 clk_40mhz<BR>END</DIV> <DIV> </DIV> <DIV>BEGIN lmb_bram_if_cntlr<BR> PARAMETER INSTANCE =3D=20 d_bram_cntrl<BR> PARAMETER HW_VER =3D 1.00.b<BR> PARAMETER = C_BASEADDR =3D=20 0x00000000<BR> PARAMETER C_HIGHADDR =3D = 0x00007FFF<BR> BUS_INTERFACE=20 SLMB =3D d_lmb<BR> BUS_INTERFACE BRAM_PORT =3D inst<BR> PORT = LMB_Clk =3D=20 clk_40mhz<BR>END</DIV> <DIV> </DIV> <DIV>BEGIN opb_pci<BR> PARAMETER INSTANCE =3D = pci<BR> PARAMETER HW_VER =3D=20 1.00.b<BR> PARAMETER C_BASEADDR =3D 0x00009000<BR> PARAMETER = C_HIGHADDR=20 =3D 0x00009FFF<BR> PARAMETER C_PCIBAR_NUM =3D 2<BR> PARAMETER=20 C_PCIBAR_LEN_0 =3D 15<BR> PARAMETER C_PCIBAR2IPIF_0 =3D=20 0x00008000<BR> PARAMETER C_PCIBAR_ENDIAN_TRANSLATE_EN_0 =3D=20 1<BR> PARAMETER C_PCI_PREFETCH_0 =3D 1<BR> PARAMETER = C_PCI_SPACETYPE_0 =3D=20 1<BR> PARAMETER C_IPIFBAR_NUM =3D 1<BR> PARAMETER = C_IPIF_HIGHADDR_0 =3D=20 0x0000FFFF<BR> PARAMETER C_IPIFBAR2PCI_0 =3D 0x0<BR> PARAMETER = C_IPIFBAR_ENDIAN_TRANSLATE_EN_0 =3D 1<BR> PARAMETER = C_IPIF_PREFETCH_0 =3D=20 1<BR> PARAMETER C_IPIF_SPACETYPE_0 =3D 1<BR> PARAMETER = C_NUM_INTERRUPTS=20 =3D 13<BR> PARAMETER C_OPB_CLK_PERIOD_PS =3D = 25000<BR> PARAMETER=20 C_CLASS_CODE =3D 0x028000<BR> PARAMETER C_DEVICE_ID =3D=20 0x9050<BR> PARAMETER C_DMA_HIGHADDR =3D = 0x0000A77F<BR> PARAMETER=20 C_DMA_CHAN_TYPE =3D 0<BR> PARAMETER C_DMA_LENGTH_WIDTH =3D=20 15<BR> PARAMETER C_DEV_MIR_ENABLE =3D 1<BR> PARAMETER = C_INCLUDE_DEV_ISC=20 =3D 1<BR> PARAMETER C_IPIFBAR_1 =3D 0x0000A600<BR> PARAMETER=20 C_IPIF_HIGHADDR_1 =3D 0x0000A61F<BR> PARAMETER C_IPIFBAR2PCI_1 =3D=20 0x0<BR> PARAMETER C_IPIFBAR_ENDIAN_TRANSLATE_EN_1 =3D = 1<BR> PARAMETER=20 C_IPIF_PREFETCH_1 =3D 1<BR> PARAMETER C_IPIF_SPACETYPE_1 =3D=20 1<BR> PARAMETER C_PCIBAR_1 =3D 0xFFFFFFF8<BR> PARAMETER = C_PCIBAR_LEN_1 =3D=20 4<BR> PARAMETER C_PCIBAR2IPIF_1 =3D 0x0000A600<BR> PARAMETER=20 C_PCIBAR_ENDIAN_TRANSLATE_EN_1 =3D 1<BR> PARAMETER C_PCI_PREFETCH_1 = =3D=20 1<BR> PARAMETER C_PCI_SPACETYPE_1 =3D 1<BR> PARAMETER = C_VENDOR_ID =3D=20 0x10B7<BR> PARAMETER C_INCLUDE_PCI_CONFIG =3D 1<BR> PARAMETER = C_REV_ID =3D=20 0x01<BR> PARAMETER C_MAX_LAT =3D 0x08<BR> PARAMETER C_MIN_GNT = =3D=20 0x03<BR> PARAMETER C_NUM_IDSEL =3D 1<BR> PARAMETER = C_DMA_BASEADDR =3D=20 0x0000A700<BR> PARAMETER C_PCIBAR_0 =3D = 0xFFFF0008<BR> PARAMETER=20 C_IPIFBAR_0 =3D 0x00008000<BR> BUS_INTERFACE MSOPB =3D = d_opb<BR> PORT=20 TRDY_N =3D pci_TRDY_N<BR> PORT OPB_Clk =3D clk_40mhz<BR> PORT = CBE =3D=20 pci_CBE<BR> PORT DEVSEL_N =3D pci_DEVSEL_N<BR> PORT FRAME_N = =3D=20 pci_FRAME_N<BR> PORT AD =3D pci_AD<BR> PORT SERR_N =3D=20 pci_SERR_N<BR> PORT IDSEL =3D pci_IDSEL<BR> PORT INTR_A =3D=20 pci_INTR_A<BR> PORT IRDY_N =3D pci_IRDY_N<BR> PORT PAR =3D=20 pci_PAR<BR> PORT GNT_N =3D pci_GNT_N<BR> PORT Freeze =3D=20 pci_Freeze<BR> PORT PCLK =3D pci_PCLK<BR> PORT STOP_N =3D=20 pci_STOP_N<BR> PORT RST_N =3D pci_RST_N<BR> PORT REQ_N =3D=20 pci_REQ_N<BR> PORT PERR_N =3D pci_PERR_N<BR>END</DIV> <DIV> </DIV> <DIV>BEGIN opb_uartlite<BR> PARAMETER INSTANCE =3D = uart<BR> PARAMETER=20 HW_VER =3D 1.00.b<BR> PARAMETER C_BASEADDR =3D = 0x0000A000<BR> PARAMETER=20 C_HIGHADDR =3D 0x0000A0FF<BR> PARAMETER C_DATA_BITS =3D = 8<BR> PARAMETER=20 C_CLK_FREQ =3D 40000000<BR> PARAMETER C_BAUDRATE =3D = 9600<BR> PARAMETER=20 C_USE_PARITY =3D 0<BR> PARAMETER C_ODD_PARITY =3D = 0<BR> BUS_INTERFACE SOPB=20 =3D d_opb<BR> PORT OPB_Clk =3D clk_40mhz<BR> PORT RX =3D=20 RS232_RX<BR> PORT TX =3D RS232_TX<BR> PORT Interrupt =3D=20 net_gnd<BR>END</DIV> <DIV> </DIV> <DIV>BEGIN opb_jtag_uart<BR> PARAMETER INSTANCE =3D=20 jtag_uart<BR> PARAMETER HW_VER =3D 1.00.b<BR> PARAMETER = C_BASEADDR =3D=20 0x0000A100<BR> PARAMETER C_HIGHADDR =3D = 0x0000A1FF<BR> BUS_INTERFACE=20 SOPB =3D d_opb<BR> PORT Interrupt =3D net_gnd<BR> PORT OPB_Clk = =3D=20 clk_40mhz<BR>END</DIV> <DIV> </DIV> <DIV>BEGIN lmb_v10<BR> PARAMETER INSTANCE =3D = d_lmb<BR> PARAMETER HW_VER=20 =3D 1.00.a<BR> PORT SYS_Rst =3D sys_rst<BR> PORT LMB_Clk =3D=20 clk_40mhz<BR>END</DIV> <DIV> </DIV> <DIV>BEGIN lmb_v10<BR> PARAMETER INSTANCE =3D = i_lmb<BR> PARAMETER HW_VER=20 =3D 1.00.a<BR> PORT SYS_Rst =3D sys_rst<BR> PORT LMB_Clk =3D=20 clk_40mhz<BR>END</DIV> <DIV> </DIV> <DIV>BEGIN opb_v20<BR> PARAMETER INSTANCE =3D = d_opb<BR> PARAMETER HW_VER=20 =3D 1.10.b<BR> PARAMETER C_BASEADDR =3D = 0xFF020000<BR> PARAMETER=20 C_HIGHADDR =3D 0xFF0201FF<BR> PARAMETER C_PROC_INTRFCE =3D = 1<BR> PORT=20 SYS_Rst =3D sys_rst<BR> PORT OPB_Clk =3D clk_40mhz<BR>END</DIV> <DIV> </DIV> <DIV>BEGIN opb_gpio<BR> PARAMETER INSTANCE =3D = led<BR> PARAMETER HW_VER=20 =3D 2.00.a<BR> PARAMETER C_BASEADDR =3D = 0x0000A200<BR> PARAMETER=20 C_HIGHADDR =3D 0x0000A2FF<BR> PARAMETER C_GPIO_WIDTH =3D=20 8<BR> BUS_INTERFACE SOPB =3D d_opb<BR> PORT OPB_Clk =3D=20 clk_40mhz<BR> PORT GPIO_IO =3D led_pin<BR>END</DIV> <DIV> </DIV> <DIV>BEGIN opb_gpio<BR> PARAMETER INSTANCE =3D = sw<BR> PARAMETER HW_VER =3D=20 2.00.a<BR> PARAMETER C_BASEADDR =3D 0x0000A300<BR> PARAMETER = C_HIGHADDR=20 =3D 0x0000A3FF<BR> PARAMETER C_GPIO_WIDTH =3D = 8<BR> BUS_INTERFACE SOPB =3D=20 d_opb<BR> PORT GPIO_IO =3D sw_pin<BR> PORT OPB_Clk =3D=20 clk_40mhz<BR>END</DIV> <DIV> </DIV> <DIV>BEGIN opb_intc<BR> PARAMETER INSTANCE =3D = intc<BR> PARAMETER HW_VER=20 =3D 1.00.c<BR> PARAMETER C_BASEADDR =3D = 0x0000A400<BR> PARAMETER=20 C_HIGHADDR =3D 0x0000A4FF<BR> PARAMETER C_IRQ_IS_LEVEL =3D=20 0<BR> BUS_INTERFACE SOPB =3D d_opb<BR> PORT OPB_Clk =3D=20 clk_40mhz<BR> PORT Intr =3D bar_int_Intr<BR> PORT Irq =3D=20 mblaze_int<BR>END</DIV> <DIV> </DIV> <DIV>BEGIN opb_interrupt_generator<BR> PARAMETER INSTANCE =3D=20 bar_int<BR> PARAMETER C_BASEADDR =3D 0x0000A600<BR> PARAMETER = C_HIGHADDR=20 =3D 0x0000A60F<BR> BUS_INTERFACE SOPB =3D d_opb<BR> PORT = opb_clk =3D=20 sys_clk<BR> PORT Interrupt =3D bar_int_Intr<BR>END</DIV> <DIV> </DIV> <DIV>BEGIN opb_bram_if_cntlr<BR> PARAMETER INSTANCE =3D=20 pk_mem<BR> PARAMETER HW_VER =3D 1.00.a<BR> PARAMETER = C_BASEADDR =3D=20 0x00008000<BR> PARAMETER C_HIGHADDR =3D 0x0000FFFF<BR>END</DIV> <DIV> </DIV> <DIV></FONT> </DIV> <BLOCKQUOTE=20 style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; = BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px"> <DIV>"seb" <<A=20 = href=3D"mailto:sebastien.longueville@fr.thalesgroup.com">sebastien.longue= ville@fr.thalesgroup.com</A>>=20 wrote in message <A=20 = href=3D"news:ee878f6.2@webx.sUN8CHnE">news:ee878f6.2@webx.sUN8CHnE</A>...= </DIV>Which=20 EDK version do you use ? <BR>Could you paste your MHS file=20 ?</BLOCKQUOTE></BODY></HTML> ------=_NextPart_000_001F_01C47311.056DD9A0--
Reply by ●July 27, 20042004-07-27
Reply by ●July 27, 20042004-07-27
"Jackson Pang" <jacpang@cisco.com> wrote in message news:<1089908158.304115@sj-nntpcache-3>...> Hello > > I'd like to know if anybody had any success in using Xilinx OPB/PCI bridge > core using EDK. I set up the project and configured all the core parameters > correctly. I also double checked the constraint file for pin assignments for > the PCI finger. The compile and programming process goes well without any > error, but I cannot even get my host PC to recognize my development board > with the PCI bitmap. I am using Avnet's Virtex II PCI Development Board. > Thanks for your input in advance.Jackson, From your other email I noticed that you are using v1_00_b of the opb pci. It was our experience with this version of the core that the PCI target read transactions will hang the PCI bus. This bug was reported Nov 2003. I did a very cursory search of the answers database, and did not see an entry on the topic. IIRC, config cycles worked okay on the core, so this is not your current problem. I would recomend that you use a more recent revision of the core than v1_00_b. I would assume that this bug is fixed by now, but you might want to ask. As we could not wait for the bugs to be fixed, we developed a PCI to PLB, and PCI to OPB bridge, with DMA (pci master) support on the PLB side. This core supports bursting on all but the OPB buses at present. We can make this available on a commercial basis. It is wrapped around the Xilinx PCI logicore, which I should note is one of the best documented, most flexible, pieces of IP we have ever used. Regards, Erik Widding. --- Birger Engineering, Inc. -------------------------------- 617.695.9233 100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.com
Reply by ●July 28, 20042004-07-28
This is a multi-part message in MIME format. ------=_NextPart_000_000D_01C4747F.6233B140 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hi Seb Avnet doesn't use EDK as far as I know and they only gave us the bitmap = of a PCIX implementation to show that the card works. I will ask them = again about whether they have done EDK implementation since we bought = the board. Thanks again. Jackson <seb> wrote in message news:ee878f6.4@webx.sUN8CHnE... It looks good.=20 Try to get a PCI design example from Avnet to underline differences ------=_NextPart_000_000D_01C4747F.6233B140 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD> <META http-equiv=3DContent-Type content=3D"text/html; = charset=3Diso-8859-1"> <META content=3D"MSHTML 6.00.2800.1400" name=3DGENERATOR> <STYLE></STYLE> </HEAD> <BODY bgColor=3D#ffffff> <DIV><FONT face=3DArial size=3D2>Hi Seb</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2>Avnet doesn't use EDK as far as I know = and they=20 only gave us the bitmap of a PCIX implementation to show that the card = works. I=20 will ask them again about whether they have done EDK implementation = since we=20 bought the board.</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2>Thanks again.</FONT></DIV> <DIV><FONT face=3DArial size=3D2>Jackson</FONT></DIV> <BLOCKQUOTE=20 style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; = BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px"> <DIV><seb> wrote in message <A=20 = href=3D"news:ee878f6.4@webx.sUN8CHnE">news:ee878f6.4@webx.sUN8CHnE</A>...= </DIV>It=20 looks good. <BR>Try to get a PCI design example from Avnet to = underline=20 differences</BLOCKQUOTE></BODY></HTML> ------=_NextPart_000_000D_01C4747F.6233B140--
Reply by ●July 28, 20042004-07-28
Hi Erik Thanks so much for your input and offer. I am working for a research group at Cal Poly and we have very limited funds. It is a learning experience for us to be able use PCI with our intelligent NIC. However, due to our license agreement with Xilinx, we cannot get any technical support to help us pin point what is wrong with our PCI/OPB core implementation. I'd also like to try implementing the OPB/PCI wrapper to the Xilinx Logicore to get a better understanding of the core. I'd like to know if you're willing to share your OPB/PCI interface wrapper implementation experience. Thanks for your help Jackson FYI - our project is on the web at http://netprl.calpoly.edu "Erik Widding" <widding@birger.com> wrote in message news:afe40eec.0407271638.28365ac6@posting.google.com...> "Jackson Pang" <jacpang@cisco.com> wrote in messagenews:<1089908158.304115@sj-nntpcache-3>...> > Hello > > > > I'd like to know if anybody had any success in using Xilinx OPB/PCIbridge> > core using EDK. I set up the project and configured all the coreparameters> > correctly. I also double checked the constraint file for pin assignmentsfor> > the PCI finger. The compile and programming process goes well withoutany> > error, but I cannot even get my host PC to recognize my developmentboard> > with the PCI bitmap. I am using Avnet's Virtex II PCI Development Board. > > Thanks for your input in advance. > > Jackson, > > From your other email I noticed that you are using v1_00_b of the > opb pci. It was our experience with this version of the core that > the PCI target read transactions will hang the PCI bus. This bug > was reported Nov 2003. I did a very cursory search of the answers > database, and did not see an entry on the topic. > > IIRC, config cycles worked okay on the core, so this is not your > current problem. I would recomend that you use a more recent > revision of the core than v1_00_b. I would assume that this bug is > fixed by now, but you might want to ask. > > As we could not wait for the bugs to be fixed, we developed a PCI > to PLB, and PCI to OPB bridge, with DMA (pci master) support on > the PLB side. This core supports bursting on all but the OPB buses > at present. We can make this available on a commercial basis. It > is wrapped around the Xilinx PCI logicore, which I should note is > one of the best documented, most flexible, pieces of IP we have > ever used. > > > Regards, > Erik Widding. > > --- > Birger Engineering, Inc. -------------------------------- 617.695.9233 > 100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.com
Reply by ●July 28, 20042004-07-28
Jackson, Support for the Universities is provided by: http://www.xilinx.com/univ/ And not through the regular Xilinx hotline system. http://xup.msu.edu/ Michigan State University is tasked with being the "University Hotline" for our hundreds of thousands of students world wide. This allows the commercial hotline to provide the best possible solutions to our 'paying customers', and also allows students to work directly with their peers who have been trained by Xilinx to answer their questions. I hope no one is confused enough (by your email domain)to think that Xilinx has a license that prevents the support of a product! Austin Jackson Pang wrote:> Hi Erik > > Thanks so much for your input and offer. I am working for a research group > at Cal Poly and we have very limited funds. It is a learning experience for > us to be able use PCI with our intelligent NIC. However, due to our license > agreement with Xilinx, we cannot get any technical support to help us pin > point what is wrong with our PCI/OPB core implementation. I'd also like to > try implementing the OPB/PCI wrapper to the Xilinx Logicore to get a better > understanding of the core. I'd like to know if you're willing to share your > OPB/PCI interface wrapper implementation experience. > > Thanks for your help > Jackson > > FYI - our project is on the web at http://netprl.calpoly.edu > > > > > "Erik Widding" <widding@birger.com> wrote in message > news:afe40eec.0407271638.28365ac6@posting.google.com... > >>"Jackson Pang" <jacpang@cisco.com> wrote in message > > news:<1089908158.304115@sj-nntpcache-3>... > >>>Hello >>> >>>I'd like to know if anybody had any success in using Xilinx OPB/PCI > > bridge > >>>core using EDK. I set up the project and configured all the core > > parameters > >>>correctly. I also double checked the constraint file for pin assignments > > for > >>>the PCI finger. The compile and programming process goes well without > > any > >>>error, but I cannot even get my host PC to recognize my development > > board > >>>with the PCI bitmap. I am using Avnet's Virtex II PCI Development Board. >>>Thanks for your input in advance. >> >>Jackson, >> >>From your other email I noticed that you are using v1_00_b of the >>opb pci. It was our experience with this version of the core that >>the PCI target read transactions will hang the PCI bus. This bug >>was reported Nov 2003. I did a very cursory search of the answers >>database, and did not see an entry on the topic. >> >>IIRC, config cycles worked okay on the core, so this is not your >>current problem. I would recomend that you use a more recent >>revision of the core than v1_00_b. I would assume that this bug is >>fixed by now, but you might want to ask. >> >>As we could not wait for the bugs to be fixed, we developed a PCI >>to PLB, and PCI to OPB bridge, with DMA (pci master) support on >>the PLB side. This core supports bursting on all but the OPB buses >>at present. We can make this available on a commercial basis. It >>is wrapped around the Xilinx PCI logicore, which I should note is >>one of the best documented, most flexible, pieces of IP we have >>ever used. >> >> >>Regards, >>Erik Widding. >> >>--- >>Birger Engineering, Inc. -------------------------------- 617.695.9233 >>100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.com > > >
