Are there any FPGA parts available today that can contain a 32-bit, free-running counter running at 1GHz and a 32-bit storage register to take a snapshot of the count and read it to a slower external interface? The Xilinx Virtex II Pro seems to go up to about 325MHz... Thanks. Dave
1GHz FPGA counters
Started by ●July 25, 2004
Reply by ●July 25, 20042004-07-25
> Are there any FPGA parts available today that can contain a 32-bit, > free-running counter running at 1GHz and a 32-bit storage register to takea> snapshot of the count and read it to a slower external interface?I doubt any FPGAs can count that fast ... not directly - you could use 4 counters running with different clocks (shifted by 90 degrees) at 250 MHz ... - you could use the Rocket-IO SerDes ... de-serialize your gate-signal and process the datawords at a lower frequency .. bye, Michael
Reply by ●July 25, 20042004-07-25
starfire wrote:> Are there any FPGA parts available today that can contain a 32-bit, > free-running counter running at 1GHz and a 32-bit storage register to take a > snapshot of the count and read it to a slower external interface? > > The Xilinx Virtex II Pro seems to go up to about 325MHz...Short answer is no. Getting a divide by 2 close to 1GHz on a room temp typical basis is probably do-able, check with Peter A. at Xilinx ? Full margin, 32bit count and capture requires carry logic and so is going to be slower. If you really want to measure time, (or create pulse widths), then FPGAs do have resources that can go under 1ns in time resolve. -jg
Reply by ●July 26, 20042004-07-26
On Mon, 26 Jul 2004 11:19:29 +1200, Jim Granville <no.spam@designtools.co.nz> wrote:>starfire wrote: >> Are there any FPGA parts available today that can contain a 32-bit, >> free-running counter running at 1GHz and a 32-bit storage register to take a >> snapshot of the count and read it to a slower external interface? >> >> The Xilinx Virtex II Pro seems to go up to about 325MHz...I've done (tiny) Johnson counters in Virtex II Pro that would go to more than twice that speed. They could be used as a prescaler for a larger binary counter. 800MHz seems to be about the limit. Perhaps the OP should wait for Virtex 4. (What about Peter Alfke's frequency counter? Didn't he claim 1GHz in V2P?) Regards, Allan.
Reply by ●July 26, 20042004-07-26
Thanks for the response. My application is for precise time correlation readings between random input pulses starting with a reset/sync pulse. The thought is if a free-running counter with 1ns resolution were reset to zero on receipt of the reset/sync pulse then a snapshot of the count made when a series of pulses are received (a separate 32-bit counter value when each pulse is received), a precise time correlation could be made from the sync to any input and from any input to any other input. The reset/sync pulse would normally be received before allowing the counter to overflow (typically about 35ms). What resources are you referring to when you say FPGAs have resources that can go under 1ns in time resolve? Dave "Jim Granville" <no.spam@designtools.co.nz> wrote in message news:SdXMc.280$zS6.50495@news02.tsnz.net...> starfire wrote: > > Are there any FPGA parts available today that can contain a 32-bit, > > free-running counter running at 1GHz and a 32-bit storage register totake a> > snapshot of the count and read it to a slower external interface? > > > > The Xilinx Virtex II Pro seems to go up to about 325MHz... > > Short answer is no. > Getting a divide by 2 close to 1GHz on a room temp typical basis is > probably do-able, check with Peter A. at Xilinx ? > > Full margin, 32bit count and capture requires carry logic and so is > going to be slower. > > If you really want to measure time, (or create pulse widths), > then FPGAs do have resources that can go under 1ns in time resolve. > > -jg >
Reply by ●July 26, 20042004-07-26
"Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:hgt8g05ihvgi86ei0hmvdi19pj7b9a6ca0@4ax.com...> On Mon, 26 Jul 2004 11:19:29 +1200, Jim Granville > <no.spam@designtools.co.nz> wrote: > > >starfire wrote: > >> Are there any FPGA parts available today that can contain a 32-bit, > >> free-running counter running at 1GHz and a 32-bit storage register totake a> >> snapshot of the count and read it to a slower external interface? > >> > >> The Xilinx Virtex II Pro seems to go up to about 325MHz... > > I've done (tiny) Johnson counters in Virtex II Pro that would go to > more than twice that speed. They could be used as a prescaler for a > larger binary counter. > > 800MHz seems to be about the limit. Perhaps the OP should wait for > Virtex 4.A few months ago Xilinx announced that they had achieved 1 GHz performance in the lab, so it's probably a couple of years away for production devices. Leon
Reply by ●July 26, 20042004-07-26
starfire wrote:> Thanks for the response. > > My application is for precise time correlation readings between random input > pulses starting with a reset/sync pulse. The thought is if a free-running > counter with 1ns resolution were reset to zero on receipt of the reset/sync > pulse then a snapshot of the count made when a series of pulses are received > (a separate 32-bit counter value when each pulse is received), a precise > time correlation could be made from the sync to any input and from any input > to any other input. The reset/sync pulse would normally be received before > allowing the counter to overflow (typically about 35ms).Sounds like a time-domain problem...> What resources are you referring to when you say FPGAs have resources that > can go under 1ns in time resolve?Consider a 250MHz freq, with 4 phases in a DLL/PLL, capture of those resolves to 1ns,but only needs to toggle at 250MHz. Or, a long simple carry chain, with many capture registers : An edge can capture to the delay quantize, so 200 chain of 200ps each, is 40ns. This will need alternate calibrate/measure, as the delays are silicon derived, so are Vcc/Temp variable. Some DLLs/DCM allow finer phase adj than 4, so 8 phase clock, and 8 copies of 125MHz counters/capture would resolve to 1ns (each IP edge). You will need to watch aperture and metastable effects in cross-clock domains, but the x8 copy scheme would allow you to check the integrity, as all counters should be within 1 count of one another. So you might read [+1][+1][+1][Whoops][+0][+0]{+0][+0] [Whoops] is a wildly variant value, that indicates the sample edge violated the [DeltaQt]+ [DeltaDt] aperture time. As a general indication of the counter speeds/width, these are from a Lattice data sheet ( not clear if these are guaranteed, or typical ) 16-bit counter 360 MHz 32-bit counter 280 MHz 64-bit counter 180 MHz -jg
Reply by ●July 26, 20042004-07-26
> What resources are you referring to when you say FPGAs have resources that > can go under 1ns in time resolve?well - there are still the RocketIOs ... You can easily reach 0.5 ns There was a thread in March - look at Message-ID: <BC8772E1.5C19%peter@xilinx.com> (with RocketIO-X you could even go further..) bye, Michael
Reply by ●July 26, 20042004-07-26
On Mon, 26 Jul 2004 08:47:28 +0200, Michael Sch�berl <MSchoeberl@ratnet.stw.uni-erlangen.de> wrote:>> What resources are you referring to when you say FPGAs have resources that >> can go under 1ns in time resolve? > >well - there are still the RocketIOs ... You can easily reach 0.5 ns >There was a thread in March - look at >Message-ID: <BC8772E1.5C19%peter@xilinx.com> > >(with RocketIO-X you could even go further..)http://groups.google.com/groups?threadm=BC8772E1.5C19%25peter%40xilinx.com will work better for most people, as very few news servers will hold a message from March. Regards, Allan.
Reply by ●July 26, 20042004-07-26
starfire wrote:> > Are there any FPGA parts available today that can contain a 32-bit, > free-running counter running at 1GHz and a 32-bit storage register to take a > snapshot of the count and read it to a slower external interface? > > The Xilinx Virtex II Pro seems to go up to about 325MHz...I am surprised that no one has mentioned that you can pipeline a counter to get much higher speeds. This takes more logic and your capture registers must also be pipelined, but you can get much higher speeds this way. Each bit of the counter has two FF outputs, one is that bit of the count and the other is the carry out to the next stage. So each bit of the counter will be one clock behind the next lower bit. It only requires a single stage of carry propogation, so longer counters do not run slower. This will run at about the same speed as a toggle FF. Ci-1 ---- ---- -------| & |--------|D Q|--- Ci +---| | | | | ---- clk---|> | +------------+ ---- ---- | |D Q|---+-------- Bi clk | | -------|> | ---- -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
