more than 58'000 false paths...

Hi Bob,
BobH <wanderingmetalhead.nospam.please@yahoo.com> wrote:
[]
> I always considered the false path declaration to be useful for handling 
> multiple clock domain issues, or getting the tool chain to ignore the 
> scan clock (or scan enable) to normal clock interaction type problems. 

Please refer to my other thread on 'path verification' to follow the 
insanity of what I've been asked to do.

> With a single clock domain, using the false path won't work from clock 
> to clock.

false paths are from clock to D.

> If you are getting 60K expansions on 50 nets, maybe reducing the 
> wildcarding would help.

Uhm, I do not think I have much of a choice if I do not want to change 
the constraint file over and over again.

> 
> Is all of your clock distribution on one of the global clock routing 
> resources? Are you using clock gating?

I haven't done any check about the clock beeing used on a single clock 
routing resource, but I guess is not since typically those chips are 
devided in quadrants and each quadrant has its own clock resource.

I'm not sure if I need to pay extra attention to quadrant crossing clocks...

> 
> 60% utilization should not be forcing the P&R tool into choices that 
> have problems. Do you have the I/O pins constrained? If so, releasing 
> the pin constraints and letting the tool pick them is a useful 
> troubleshooting method.

There are no I/O pins at all, the design is meant to be used as a block 
since we cannot afford to re-do the exercise everytime we integrate the 
module within another project.

> This is about all the ideas I have at this point.

Thanks for sharing them.

Al