Using FPGA as dual ported ram

To interface a fast sampling ADC to a CPU I'm considering to use a fifo
or dual ported ram and a small controlling CPLD. Cypress has a nice
offering of fifos and dp-rams, but looking at the prices of 512kb
density parts I got a bit of a shock: $75 for the fifo and $45 for the
dp-ram. That's in single quantity, but they don't go down fast either:
$30/1000+ for the dp-ram. :-(
(prices from cypress website)

For less money, you can have a Xilinx spartan-6 (XC6SLX9-2TQG144C $20/1+
$14/1000+) with 512kB of Block ram. And you get your controlling 'CPLD'
for free. OK you still need a config memory.
(prices from avnet website)

Can you just connect one side of the block ram to IO pins and read that
from a CPU as if it where a dp-ram? Other side interface would even be
simpler as you can keep it internal.

Am I missing something here or is it really that simple?
(And yes, I do realize  I have to program the FPGA to perform the
required function ;-) )

Sample rate is not extremely high (10MSPS), but too fast for the CPU to
read on interrupts directly. There may be other options, still
investigating.

-- 
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)

One man's constant is another man's variable.
		-- A.J. Perlis

On Tue, 08 Jul 2014 16:43:32 +0200
Stef <stef33d@yahooI-N-V-A-L-I-D.com.invalid> wrote:

> 
> Can you just connect one side of the block ram to IO pins and read that
> from a CPU as if it where a dp-ram? Other side interface would even be
> simpler as you can keep it internal.
> 
> Am I missing something here or is it really that simple?
> (And yes, I do realize  I have to program the FPGA to perform the
> required function ;-) )
> 

You'll find that the CPU memory bus interface and the FPGA BRAM
interface don't 100% match up, so you have to put a bit of glue logic
(in the FPGA fabric) in the middle, but more yes than no.

It'll be things like, the BRAM is going to be synchronous whereas the
memory bus expects to be asynch, so you'll want to latch the membus
signals and resynchronize the strobes (CS, WE, OE) to make sure you
don't have any glitches, etc.  But yeah, you're talking about
instantianting a BRAM from the library and throwing a few dozen lines
of code around it.

-- 
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.

Hi,

Maybe this helps,an FPGA module with a mid-size Spartan 6 LX 75 device and
lots of IOs:
http://numato.com/saturn-spartan-6-fpga-development-board-with-ddr-sdram
Best enjoyed with a JTAG programmer (i.e. Xilinx "USB" JTAG from ebay) as
it doesn't support direct FPGA programming via USB, but reprogramming goes
through the somewhat slower Flash memory.

AFAIK, also the larger LX 75 can be programmed without paying for a
license. A google search "Spartan 6 LX 75 board" shows some boards but I
haven't tried any of those.

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

>> Best enjoyed with a JTAG programmer 
correction: one post on the linked page states that it can now be
programmed directly => no need for JTAG.
	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Stef wrote:
> To interface a fast sampling ADC to a CPU I'm considering to use a fifo
> or dual ported ram and a small controlling CPLD. Cypress has a nice
> offering of fifos and dp-rams, but looking at the prices of 512kb
> density parts I got a bit of a shock: $75 for the fifo and $45 for the
> dp-ram. That's in single quantity, but they don't go down fast either:
> $30/1000+ for the dp-ram. :-(
> (prices from cypress website)
> 
> For less money, you can have a Xilinx spartan-6 (XC6SLX9-2TQG144C $20/1+
> $14/1000+) with 512kB of Block ram. And you get your controlling 'CPLD'
> for free. OK you still need a config memory.
> (prices from avnet website)

You wrote 512kB which usually means kilobytes.  The LX9 has 512 Kb which
means kilobits, or 64 kilobytes.  If you really needed 512 kilobytes,
you would need a much larger part: Spartan 6 LX100, or Artix-7 100T.
On the other hand you wrote 512kb when you talked about Cypress parts...

> Can you just connect one side of the block ram to IO pins and read that
> from a CPU as if it where a dp-ram? Other side interface would even be
> simpler as you can keep it internal.
> 
> Am I missing something here or is it really that simple?
> (And yes, I do realize  I have to program the FPGA to perform the
> required function ;-) )
> 
> Sample rate is not extremely high (10MSPS), but too fast for the CPU to
> read on interrupts directly. There may be other options, still
> investigating.
> 

As others have said, the work involved is not a lot and depends on
the CPU bus.  I suspect that the "small controlling CPLD" code would
include pretty much the same logic you'd plug into the FPGA other
than the DP RAM.

-- 
Gabor

In comp.arch.fpga,
Rob Gaddi <rgaddi@technologyhighland.invalid> wrote:
> On Tue, 08 Jul 2014 16:43:32 +0200
> Stef <stef33d@yahooI-N-V-A-L-I-D.com.invalid> wrote:
>
>> 
>> Can you just connect one side of the block ram to IO pins and read that
>> from a CPU as if it where a dp-ram? Other side interface would even be
>> simpler as you can keep it internal.
>> 
>> Am I missing something here or is it really that simple?
>> (And yes, I do realize  I have to program the FPGA to perform the
>> required function ;-) )
>> 
>
> You'll find that the CPU memory bus interface and the FPGA BRAM
> interface don't 100% match up, so you have to put a bit of glue logic
> (in the FPGA fabric) in the middle, but more yes than no.
>
> It'll be things like, the BRAM is going to be synchronous whereas the
> memory bus expects to be asynch, so you'll want to latch the membus
> signals and resynchronize the strobes (CS, WE, OE) to make sure you
> don't have any glitches, etc.  But yeah, you're talking about
> instantianting a BRAM from the library and throwing a few dozen lines
> of code around it.

OK, still need the resync, no direct connect to BRAM. So it will be
very similar to a simple I/O register interface that I did years ago in
a spartan-3. Thanks for the heads up.

-- 
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)

"Plan to throw one away.  You will anyway."
- Fred Brooks, "The Mythical Man Month"

In comp.arch.fpga,
GaborSzakacs <gabor@alacron.com> wrote:
> Stef wrote:
>> To interface a fast sampling ADC to a CPU I'm considering to use a fifo
>> or dual ported ram and a small controlling CPLD. Cypress has a nice
>> offering of fifos and dp-rams, but looking at the prices of 512kb
>> density parts I got a bit of a shock: $75 for the fifo and $45 for the
>> dp-ram. That's in single quantity, but they don't go down fast either:
>> $30/1000+ for the dp-ram. :-(
>> (prices from cypress website)
>> 
>> For less money, you can have a Xilinx spartan-6 (XC6SLX9-2TQG144C $20/1+
>> $14/1000+) with 512kB of Block ram. And you get your controlling 'CPLD'
>> for free. OK you still need a config memory.
>> (prices from avnet website)
>
> You wrote 512kB which usually means kilobytes.  The LX9 has 512 Kb which
> means kilobits, or 64 kilobytes.  If you really needed 512 kilobytes,
> you would need a much larger part: Spartan 6 LX100, or Artix-7 100T.
> On the other hand you wrote 512kb when you talked about Cypress parts...

Sorry for the typo, the second should also have been "kb", so the LX9
should be OK.

I wouldn't dare looking up the price of a cypress 512kB FIFO after what
I saw on their website earlier today. ;-)


-- 
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)

Asynchronous inputs are at the root of our race problems.
		-- D. Winker and F. Prosser

On Tuesday, July 8, 2014 4:36:34 PM UTC-5, Stef wrote:
> I wouldn't dare looking up the price of a cypress 512kB FIFO after what I saw on their website earlier today. ;-) 

Don't overlook the cost of the power supply regulators to run the FPGA.

It may still be good deal, but maybe just not quite as good...

Andy

In comp.arch.fpga,
jonesandy@comcast.net <jonesandy@comcast.net> wrote:
> On Tuesday, July 8, 2014 4:36:34 PM UTC-5, Stef wrote:
>> I wouldn't dare looking up the price of a cypress 512kB FIFO after what I saw on their website earlier today. ;-) 
>
> Don't overlook the cost of the power supply regulators to run the FPGA.
>
> It may still be good deal, but maybe just not quite as good...

Good point. I had a quick look and it doesn't seem too bad. I already
need a 3.3V and a 1.2V for the CPU so only an additional 2.5V if I need
to use LVDS_25. Just need to allow for the extra current draw.

-- 
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)

Pick another fortune cookie.

On 08/07/2014 15:43, Stef wrote:
> To interface a fast sampling ADC to a CPU I'm considering to use a fifo
> or dual ported ram and a small controlling CPLD. Cypress has a nice
> offering of fifos and dp-rams, but looking at the prices of 512kb
> density parts I got a bit of a shock: $75 for the fifo and $45 for the
> dp-ram. That's in single quantity, but they don't go down fast either:
> $30/1000+ for the dp-ram. :-(
> (prices from cypress website)
>
> For less money, you can have a Xilinx spartan-6 (XC6SLX9-2TQG144C $20/1+
> $14/1000+) with 512kB of Block ram. And you get your controlling 'CPLD'
> for free. OK you still need a config memory.
> (prices from avnet website)

Just a thought but I use the CPU and it's memory to store the config 
information. It's not difficult to program a JTAG interface if you have 
a few spare I/O pins to eliminate config memory.

> Can you just connect one side of the block ram to IO pins and read that
> from a CPU as if it where a dp-ram? Other side interface would even be
> simpler as you can keep it internal.
>
> Am I missing something here or is it really that simple?
> (And yes, I do realize  I have to program the FPGA to perform the
> required function ;-) )
>
> Sample rate is not extremely high (10MSPS), but too fast for the CPU to
> read on interrupts directly. There may be other options, still
> investigating.

I'm left wondering if you want a Dual Port RAM, or a FIFO.

They are different beasts but the FIFO would probably be best suited to 
an FPGA as it uses less pins and the data predictable.

-- 
Mike Perkins
Video Solutions Ltd
www.videosolutions.ltd.uk