Generating a desired synthesizable binary pulse train on FPGA using VHDL

Hello Everyone 
 
I am new to VHDL programming and FPGA.
I have a Virtex - 4 FPGA and I wish to generate a  binary pulse train of 16
pulses from FPGA using VHDL programming. My desired pulse train will be
like "1011100111101110". (min pulse width should be 30ns).
I have a clock of 100 MHz and I am able to divide the clock frequency to
get the clock of 10MHz (clock frequency required for my application). Also
I am aware of the fact that "Wait for" statement can not be used for
synthesizing as it can only be used for test bench and simulation purposes.

 
So I am struggling with this problem. I am wondering if I can use "after
Xns" command in my VHDL code or if there is any other way to do it. 
 
I will be very thankful if any feedback or advice is provided. Your
response will truly be appreciated. Kindly provide your valuable
suggestions. 
 
Thanking you
Regards
Chaitanya Mauskar

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On 7/22/2014 12:49 PM, chaitanya163 wrote:
> Hello Everyone
>
> I am new to VHDL programming and FPGA.
> I have a Virtex - 4 FPGA and I wish to generate a  binary pulse train of 16
> pulses from FPGA using VHDL programming. My desired pulse train will be
> like "1011100111101110". (min pulse width should be 30ns).
> I have a clock of 100 MHz and I am able to divide the clock frequency to
> get the clock of 10MHz (clock frequency required for my application). Also
> I am aware of the fact that "Wait for" statement can not be used for
> synthesizing as it can only be used for test bench and simulation purposes.
>
>
> So I am struggling with this problem. I am wondering if I can use "after
> Xns" command in my VHDL code or if there is any other way to do it.
>
> I will be very thankful if any feedback or advice is provided. Your
> response will truly be appreciated. Kindly provide your valuable
> suggestions.

In order to use an HDL (Hardware Description Language) you need to 
understand hardware enough that you can then use the HDL to describe it. 
  Think about how you would do this in hardware if you were drawing a 
schematic.  Then you can figure out how to describe that circuit in 
hardware.

So how would you design a circuit using gates and FFs to do this task?

-- 

Rick

Hi,

I can give you a quick-and-dirty skeleton in Verilog, just to get you
started.

module myPulse(input wire clk, input wire rst, output wire sig);

always @(posedge clk) begin

end

endmodule


>On 7/22/2014 12:49 PM, chaitanya163 wrote:
>> Hello Everyone
>>
>> I am new to VHDL programming and FPGA.
>> I have a Virtex - 4 FPGA and I wish to generate a  binary pulse train of
16
>> pulses from FPGA using VHDL programming. My desired pulse train will be
>> like "1011100111101110". (min pulse width should be 30ns).
>> I have a clock of 100 MHz and I am able to divide the clock frequency
to
>> get the clock of 10MHz (clock frequency required for my application).
Also
>> I am aware of the fact that "Wait for" statement can not be used for
>> synthesizing as it can only be used for test bench and simulation
purposes.
>>
>>
>> So I am struggling with this problem. I am wondering if I can use
"after
>> Xns" command in my VHDL code or if there is any other way to do it.
>>
>> I will be very thankful if any feedback or advice is provided. Your
>> response will truly be appreciated. Kindly provide your valuable
>> suggestions.
>
>In order to use an HDL (Hardware Description Language) you need to 
>understand hardware enough that you can then use the HDL to describe it. 
>  Think about how you would do this in hardware if you were drawing a 
>schematic.  Then you can figure out how to describe that circuit in 
>hardware.
>
>So how would you design a circuit using gates and FFs to do this task?
>
>-- 
>
>Rick
>	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Hi,

(browser got trigger-happy, ignore my unfinished previous post if there is
any)

here's a quick-and-dirty skeleton in Verilog. There are many ways how to
approach this, for example use a state machine if it needs to be more
complex.

This one will load "1" to the output as long as rst is asserted. When rst
goes low, the output will play back the sequence and continue with 0.

module myPulse(input wire clk, input wire rst, output wire pulseOut);

reg [15:0]  myReg = 0;
assign pulseOut = myReg[15];

always @(posedge clk) begin
if (rst) begin
myReg <= 16'b1011100111101110;
end else begin
myReg <= myReg << 1;
end
end
endmodule
	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

rickman <gnuarm@gmail.com> wrote:
> On 7/22/2014 12:49 PM, chaitanya163 wrote:

>> I am new to VHDL programming and FPGA.

(snip)
>> So I am struggling with this problem. I am wondering if I can use "after
>> Xns" command in my VHDL code or if there is any other way to do it.

(snip)

> In order to use an HDL (Hardware Description Language) you need to 
> understand hardware enough that you can then use the HDL to describe it. 
>  Think about how you would do this in hardware if you were drawing a 
> schematic.  Then you can figure out how to describe that circuit in 
> hardware.

I used to say that you should think about how you would built it using
TTL gates, but maybe not everyone knows about TTL by now.

You want to think about AND gates and flip-flops. For problems like
yours, the most important part could be a shift register, which 
is a series of flip-flops.


-- glen

chaitanya163 wrote:



> My desired pulse train will be
> like "1011100111101110". (min pulse width should be 30ns).
> I have a clock of 100 MHz and I am able to divide the clock frequency to
> get the clock of 10MHz (clock frequency required for my application). 
You will not be able to get 30 ns pulses with a 10 MHz clock.
At least one part of your logic will have to run at a higher clock
rate.  If you run the logic at 100 MHz, then you will have 10 ns
resolution on the bit timing.  You could have a 4-bit counter
running at 100 MHz/3 = 33 MHz or 30 ns period, and the desired bit
pattern entered into a 16:1 multiplexer.  The counter selects the
inputs in the proper sequence to the multiplexer.  Of course, the
synthesis tools will do a massive optimization of your description
and probably reduce it to about 5 LUTs or so.

Jon

mnentwig wrote:

> Hi,
> 
> (browser got trigger-happy, ignore my unfinished previous post if there is
> any)
> 
> here's a quick-and-dirty skeleton in Verilog. There are many ways how to
> approach this, for example use a state machine if it needs to be more
> complex.
> 
> This one will load "1" to the output as long as rst is asserted. When rst
> goes low, the output will play back the sequence and continue with 0.
> 
> module myPulse(input wire clk, input wire rst, output wire pulseOut);
> 
> reg [15:0]  myReg = 0;
> assign pulseOut = myReg[15];
> 
> always @(posedge clk) begin
> if (rst) begin
> myReg <= 16'b1011100111101110;
> end else begin
> myReg <= myReg << 1;
> end
> end
> endmodule
Ummm, that looks like Verilog, the OP requested VHDL.  While the
VHDL would not be vastly different, I don't think you can do the
<< operator quite so concisely in VHDL.  I think you can do a
loop over the bits and assign myReg<n> <- myReg<n+1>

Jon

Le mardi 22 juillet 2014 16:27:41 UTC-3, Jon Elson a =E9crit=A0:
> chaitanya163 wrote:
>
> You will not be able to get 30 ns pulses with a 10 MHz clock.
>=20
> At least one part of your logic will have to run at a higher clock
>=20
> rate.  If you run the logic at 100 MHz, then you will have 10 ns
>=20
> resolution on the bit timing.

I think 30ns is the minimum pulse size - it may be larger. If so, 10MHz wil=
l meet his specifications.

On 7/22/2014 3:30 PM, Jon Elson wrote:
> mnentwig wrote:
>
>> Hi,
>>
>> (browser got trigger-happy, ignore my unfinished previous post if there is
>> any)
>>
>> here's a quick-and-dirty skeleton in Verilog. There are many ways how to
>> approach this, for example use a state machine if it needs to be more
>> complex.
>>
>> This one will load "1" to the output as long as rst is asserted. When rst
>> goes low, the output will play back the sequence and continue with 0.
>>
>> module myPulse(input wire clk, input wire rst, output wire pulseOut);
>>
>> reg [15:0]  myReg = 0;
>> assign pulseOut = myReg[15];
>>
>> always @(posedge clk) begin
>> if (rst) begin
>> myReg <= 16'b1011100111101110;
>> end else begin
>> myReg <= myReg << 1;
>> end
>> end
>> endmodule
> Ummm, that looks like Verilog, the OP requested VHDL.  While the
> VHDL would not be vastly different, I don't think you can do the
> << operator quite so concisely in VHDL.  I think you can do a
> loop over the bits and assign myReg<n> <- myReg<n+1>

I'm sure that would work, but I find constructing a loop to be a bit 
wordy.  Here is a one line shift register.

   myReg <= myReg(myReg'high-1 downto 0) & '0';

That's not so bad is it?

However, this is not an efficient use of resources in an FPGA using up 
16 FFs along with the control logic, if any.  If it were any larger I 
would use a direct address of an array constant would use a four bit 
counter and a single LUT used as memory.

   constant SerialDataLength : integer := 16;
   constant SerialData : unsigned (SerialDataLength-1 downto 0) :=
     {'0', '1', '0', '1', '0', '1', '0', '1',
      '0', '1', '0', '1', '0', '1', '0', '1'};
   signal AddrReg : integer range 0 to SerialDataLength-1;
   signal Start : std_logic;
   signal CntrEn : std_logic;

   AddrGen : process (clk, rst) begin
     if (rst  = '1') then
       Start <= '1';
       CntrEn <= '0';
       AddrReg <= 0;
     elsif (rising_edge(clk)) then
       CntrEn <= Start;

       if (AddrReg = SerialDataLength-1) then
         Start <= '0';
         CntrEn <= '0';
       end if;

       if (CntrEn = '1') then
         AddrReg <= (AddrReg + 1) mod SerialDataLength;
       end if;
     end if;
   end process AddrGen ;

   Dout <= SerialData (AddrReg) when (Start or Stop = '0') else '0';

This should give you four FF/LUTs for the address register, three for 
the control logic and one for the mux selecting the output for a total 
of seven LUT/FFs, less than half of what it takes for the shift 
register.  For longer lengths of shift register the savings are more 
pronounced.

-- 

Rick

On Tue, 22 Jul 2014 18:56:05 +0000, glen herrmannsfeldt wrote:

> I used to say that you should think about how you would built it using
> TTL gates, but maybe not everyone knows about TTL by now.

Indeed. :)