Over the years I have taught myself Verilog and VHDL, and although I am qui= te comfortable with Verilog, I feel as though my VHDL designs are just not = as tight as they should be. In pursuit of self-improvement, I am trying to= find "real world" examples of professional VHDL designs that I can glean f= or hints on how to make my designs better. I have read many, many books and= analyzed some projects on opencores, but everything that I have seen seems= a bit lacking. I am hoping that the comp.arch.fpga community might share = a few examples of solid VHDL designs that I can review. Incomplete designs = are fine, as long as I can get a feel for how you are accomplishing things.= Bear in mind that I will not critique your design, and am not interested i= n participating in The Great HDL Debate MMXIV: Part XXIII. I need to contin= ue to use both VHDL and Verilog.
Professional VHDL Examples?
Started by ●July 31, 2014
Reply by ●July 31, 20142014-07-31
Are you familiar with Open Cores? www.opencores.org. They have a large co= llection of really some really well designed and some really not-so-well de= signed cores in both VHDL and Verilog. =20 Here's a link to a few VHDL modules that are pretty decent. I'm not sure h= ow complicated of a design you're looking for, but these are supported by t= estbenches so you can get a feel for how to write a testbench in VHDL. http://www.nandland.com/vhdl/modules/index.html On Thursday, July 31, 2014 12:34:52 PM UTC-4, wab...@gmail.com wrote:> Over the years I have taught myself Verilog and VHDL, and although I am q=uite comfortable with Verilog, I feel as though my VHDL designs are just no= t as tight as they should be. In pursuit of self-improvement, I am trying = to find "real world" examples of professional VHDL designs that I can glean= for hints on how to make my designs better. I have read many, many books a= nd analyzed some projects on opencores, but everything that I have seen see= ms a bit lacking. I am hoping that the comp.arch.fpga community might shar= e a few examples of solid VHDL designs that I can review. Incomplete design= s are fine, as long as I can get a feel for how you are accomplishing thing= s. Bear in mind that I will not critique your design, and am not interested= in participating in The Great HDL Debate MMXIV: Part XXIII. I need to cont= inue to use both VHDL and Verilog.
Reply by ●July 31, 20142014-07-31
On Thu, 31 Jul 2014 09:34:52 -0700, wabac0 wrote:> Over the years I have taught myself Verilog and VHDL, and although I am > quite comfortable with Verilog, I feel as though my VHDL designs are > just not as tight as they should be. In pursuit of self-improvement, I > am trying to find "real world" examples of professional VHDL designs > that I can glean for hints on how to make my designs better. I have read > many, many books and analyzed some projects on opencores, but everything > that I have seen seems a bit lacking. I am hoping that the > comp.arch.fpga community might share a few examples of solid VHDL > designs that I can review. Incomplete designs are fine, as long as I can > get a feel for how you are accomplishing things. Bear in mind that I > will not critique your design, and am not interested in participating in > The Great HDL Debate MMXIV: Part XXIII. I need to continue to use both > VHDL and Verilog."Professional" as in "took money for it" or as in "a good example for us all"? -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Reply by ●August 1, 20142014-08-01
On Thu, 31 Jul 2014 09:34:52 -0700, wabac0 wrote:> Over the years I have taught myself Verilog and VHDL, and although I am > quite comfortable with Verilog, I feel as though my VHDL designs are > just not as tight as they should be. In pursuit of self-improvement, I > am trying to find "real world" examples of professional VHDL designs > that I can glean for hints on how to make my designs better. I have read > many, many books and analyzed some projects on opencores, but everything > that I have seen seems a bit lacking. I am hoping that the > comp.arch.fpga community might share a few examples of solid VHDL > designs that I can review. Incomplete designs are fine, as long as I can > get a feel for how you are accomplishing things. Bear in mind that I > will not critique your design, and am not interested in participating in > The Great HDL Debate MMXIV: Part XXIII. I need to continue to use both > VHDL and Verilog.Here's an example of mine from 2002 or so. http://fractional-divider.tripod.com/fracn20.zip It shows how to use VHDL in a way that would be difficult to mimic in Verilog, and may seem strange to Verilog coders. As such, it may be useful as a learning exercise. I have a Verilog version on that same web page, but it uses a Perl script to write the Verilog, customised by some command line parameters. The VHDL version customises itself from its generics at elaboration time. Most of the code consists of functions that in many cases use floating point numbers to produce a bunch of constants that control the (relatively small) chunk of RTL at the bottom of the file. BTW, it isn't representative of code I write now, but it is still useful as a tool torture test. Regards, Allan
Reply by ●August 1, 20142014-08-01
On 7/31/2014 7:24 PM, Tim Wescott wrote:> On Thu, 31 Jul 2014 09:34:52 -0700, wabac0 wrote: > >> Over the years I have taught myself Verilog and VHDL, and although I am >> quite comfortable with Verilog, I feel as though my VHDL designs are >> just not as tight as they should be. In pursuit of self-improvement, I >> am trying to find "real world" examples of professional VHDL designs<snip>> "Professional" as in "took money for it" or as in "a good example for us > all"? >Good point - although slightly snarky :)
Reply by ●August 1, 20142014-08-01
Russell <russellmerrick@gmail.com> writes:> Are you familiar with Open Cores? www.opencores.org. They have a large collection of really some really well designed and some > really not-so-well designed cores in both VHDL and Verilog. > > Here's a link to a few VHDL modules that are pretty decent. I'm not sure how complicated of a design you're looking for, but these > are supported by testbenches so you can get a feel for how to write a testbench in VHDL. > > http://www.nandland.com/vhdl/modules/index.htmlIn the spirit of Tim's comment, http://www.nandland.com/vhdl/modules/module-fifo-regs-with-flags.html I'm not sure that a testbench that consists of multiple pasted "wait until r_clock = '1'" statements and no code to actually check the operation of the module under test would count as "a good example for us all"... Unfortunately, I'm not aware of much else I can point you at that's very complete. Most pro-grade code will be proprietary, there's isn't anywhere near as much open-source VHDL code, and most (IMHO) majors on functionality rather than development style. I have a( sadly incomplete - it's a spare time activity, and that's in short supply!) VHDL-based image processing tutorial. The VHDL part has only reached the stage of reading a PGM file into a testbench, but it may be of interest: http://parallelpoints.com/reading-image-files-with-vhdl-part-1-again/ Code can be found here: https://github.com/martinjthompson/image_processing_examples/tree/master/hdl (I should point out that this code has nothing to do with my employer, it's all my own work.) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware
Reply by ●August 1, 20142014-08-01
Have you looked at the sources for Leon 3 and the rest of the GR Lib components? They seemed like good examples to me. http://www.gaisler.com/index.php/downloads/leongrlib --Jecel
Reply by ●August 13, 20142014-08-13
On Friday, 1 August 2014 13:53:42 UTC+2, Allan Herriman wrote:> On Thu, 31 Jul 2014 09:34:52 -0700, wabac0 wrote: >=20 >=20 >=20 > > Over the years I have taught myself Verilog and VHDL, and although I am >=20 > > quite comfortable with Verilog, I feel as though my VHDL designs are >=20 > > just not as tight as they should be. In pursuit of self-improvement, I >=20 > > am trying to find "real world" examples of professional VHDL designs >=20 > > that I can glean for hints on how to make my designs better. I have rea=d>=20 > > many, many books and analyzed some projects on opencores, but everythin=g>=20 > > that I have seen seems a bit lacking. I am hoping that the >=20 > > comp.arch.fpga community might share a few examples of solid VHDL >=20 > > designs that I can review. Incomplete designs are fine, as long as I ca=n>=20 > > get a feel for how you are accomplishing things. Bear in mind that I >=20 > > will not critique your design, and am not interested in participating i=n>=20 > > The Great HDL Debate MMXIV: Part XXIII. I need to continue to use both >=20 > > VHDL and Verilog. >=20 >=20 >=20 >=20 >=20 > Here's an example of mine from 2002 or so. >=20 >=20 >=20 > http://fractional-divider.tripod.com/fracn20.zip >=20 >=20 >=20 > It shows how to use VHDL in a way that would be difficult to mimic in=20 >=20 > Verilog, and may seem strange to Verilog coders. As such, it may be=20 >=20 > useful as a learning exercise. >=20 >=20 >=20 > I have a Verilog version on that same web page, but it uses a Perl script==20>=20 > to write the Verilog, customised by some command line parameters. The=20 >=20 > VHDL version customises itself from its generics at elaboration time. >=20 >=20 >=20 > Most of the code consists of functions that in many cases use floating=20 >=20 > point numbers to produce a bunch of constants that control the=20 >=20 > (relatively small) chunk of RTL at the bottom of the file. >=20 >=20 >=20 > BTW, it isn't representative of code I write now, but it is still useful==20>=20 > as a tool torture test. >=20 >=20 >=20 > Regards, >=20 > AllanI'm interested in looking at this, but when I click on the link I get the f= ollowing message: This file is hosted by Tripod, a Lycos=AENetwork Site, and is not available= for download. Please check out Tripod's Help system for more information a= bout Remote Loading and our Remote Loading policy.
Reply by ●August 13, 20142014-08-13
On Wed, 13 Aug 2014 00:18:49 -0700, ajpkane wrote:> On Friday, 1 August 2014 13:53:42 UTC+2, Allan Herriman wrote: >> On Thu, 31 Jul 2014 09:34:52 -0700, wabac0 wrote: >> >> >> >> > Over the years I have taught myself Verilog and VHDL, and although I >> > am >> >> > quite comfortable with Verilog, I feel as though my VHDL designs are >> >> > just not as tight as they should be. In pursuit of self-improvement, >> > I >> >> > am trying to find "real world" examples of professional VHDL designs >> >> > that I can glean for hints on how to make my designs better. I have >> > read >> >> > many, many books and analyzed some projects on opencores, but >> > everything >> >> > that I have seen seems a bit lacking. I am hoping that the >> >> > comp.arch.fpga community might share a few examples of solid VHDL >> >> > designs that I can review. Incomplete designs are fine, as long as I >> > can >> >> > get a feel for how you are accomplishing things. Bear in mind that I >> >> > will not critique your design, and am not interested in participating >> > in >> >> > The Great HDL Debate MMXIV: Part XXIII. I need to continue to use >> > both >> >> > VHDL and Verilog. >> >> >> >> >> >> Here's an example of mine from 2002 or so. >> >> >> >> http://fractional-divider.tripod.com/fracn20.zip >> >> >> >> It shows how to use VHDL in a way that would be difficult to mimic in >> >> Verilog, and may seem strange to Verilog coders. As such, it may be >> >> useful as a learning exercise. >> >> >> >> I have a Verilog version on that same web page, but it uses a Perl >> script >> >> to write the Verilog, customised by some command line parameters. The >> >> VHDL version customises itself from its generics at elaboration time. >> >> >> >> Most of the code consists of functions that in many cases use floating >> >> point numbers to produce a bunch of constants that control the >> >> (relatively small) chunk of RTL at the bottom of the file. >> >> >> >> BTW, it isn't representative of code I write now, but it is still >> useful >> >> as a tool torture test. >> >> >> >> Regards, >> >> Allan > > I'm interested in looking at this, but when I click on the link I get > the following message: > > This file is hosted by Tripod, a Lycos®Network Site, and is not > available for download. Please check out Tripod's Help system for more > information about Remote Loading and our Remote Loading policy.I just tested it and it downloaded fine for me. It sounds like a problem at your end. I emailed a copy to the email address in the header of your post. Regards, Allan
