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LVDS problem - Black magic anyone?

Started by Unknown August 9, 2014
I have an LVDS related issue that drives me crazy:

There are two boards with a FPGA that are connected by a ca. 30cm cable. On=
ly 6 wirea are used:
GND + Power
LVDS (with embedded clock), 720Mbps
UART (Rxd + Txd)
(The cable is unshielded for flexibility reasons)

The cable is a "flat Ethernet cable" with 4 twisted pairs, one pair is unus=
ed, one pair is LVDS, one pair is GND + Rxd and the last is Power + TxD.

Most cables work fine with a low error rate. However, some cables of the sa=
me batch have an excessive error rate. These cables have no visible differe=
nce to the good cables.

The end of the cables have the outer isolation removed for about 5cm, the L=
VDS pair is twisted also for this 5cm, the other wires are straight crimped=
 to the connector.

Now the strange behavior: When touching the cable at some positions by hand=
, the bad cables are suddenly perfect or at least much better. And the even=
 stranger thing: When touching at the last 5cm, it is NOT the touching of t=
he LVDS pair that makes the difference, but the touching the GND/Power/Uart=
 wires! This can be observed on both sides of the cable.

It is really only "the hand" that makes the difference, strapping together =
the wires does not help. It does also not look like a mechanical problem of=
 the cable.

I tried changing and even removing the termination resistors, this did not =
change the behavior at all. I have changed both boards, it is really the ca=
ble that makes the difference.

Has anybody an idea what the reason of this behavior could be?

Regards,

Thomas
thomas.entner99@gmail.com wrote:
> I have an LVDS related issue that drives me crazy: > > There are two boards with a FPGA that are connected by a ca. 30cm cable. > Only 6 wirea are used: > GND + Power > LVDS (with embedded clock), 720Mbps > UART (Rxd + Txd) > (The cable is unshielded for flexibility reasons) > > The cable is a "flat Ethernet cable" with 4 twisted pairs, one pair is > unused, one pair is LVDS, one pair is GND + Rxd and the last is Power + > TxD. > > Most cables work fine with a low error rate. However, some cables of the > same batch have an excessive error rate. These cables have no visible > difference to the good cables.
What category cable is it? Even cat6 or cat6a aren't intended for use beyond 500MHz. While there's less loss because the cable is shorter, it's worth looking up the loss curves and doing the calculation. You have checked that the 'flat' cable does actually contain twisted pairs? What's the position of the ground with respect to the LVDS pair? Is it adjacent, or further away? Are these direct electrical connections, or is there any signal isolation? Is the spare pair floating? What's the grounding arrangements of both boards? Is this the only ground connection between them? How are they powered? Do they come from the same AC source, or different sources? What's the arrangement of earths, and any possibility they could be on different AC phases? What are you driving the RXD/TXD signals with? Do you know their rise time? For that matter, do you know the rise time of the LVDS signals? What are you using for an LVDS receiver? (Any equalisation?) What's the encoding on the wire (8b/10b, Manchester, etc)?
> I tried changing and even removing the termination resistors, this did not > change the behavior at all. I have changed both boards, it is really the > cable that makes the difference.
Have you looked at the signal on a scope? Where did the 'termination resistors' come from? How did you decide what topology and what values to use?
> Has anybody an idea what the reason of this behavior could be?
Some ideas: 1. You're changing the capacitance of the cable by touching it 2. You're creating a capacitive path to ground through your body 3. You're changing the topology of the inductive loop between an LVDS line and ground 4. You're coupling other signals into the LVDS pair (eg RXD), especially if the twists have ended up aligned 5. The signal has higher frequency components than you think and these are messing up the receiver. Extra capacitance by touching increases their loss, enough for the receiver to cope 6. The cable is simply too lossy at the frequency you're using 7. You have a grounding issue with the setup 8. The line isn't terminated correctly so you're getting reflections which interfere with the signal Do you have a network analyser available? Looking at the insertion loss of the cable over a range of frequencies may tell you something about what's going on. I've done a lot of work with SATA cables. Bottom line is, some are just cheap and simply don't work. SATA error recovery is enough to mask many of the problems when used in a PC, so nobody notices. Theo
> > I have an LVDS related issue that drives me crazy: > >=20 > > There are two boards with a FPGA that are connected by a ca. 30cm cable=
.
> > Only 6 wirea are used: > > GND + Power > > LVDS (with embedded clock), 720Mbps > > UART (Rxd + Txd) > > (The cable is unshielded for flexibility reasons) > >=20 > > The cable is a "flat Ethernet cable" with 4 twisted pairs, one pair is > > unused, one pair is LVDS, one pair is GND + Rxd and the last is Power + > > TxD. > >=20 > > Most cables work fine with a low error rate. However, some cables of th=
e
> > same batch have an excessive error rate. These cables have no visible > > difference to the good cables. >=20 >=20 > What category cable is it?
CAT5e (UTP)
> Even cat6 or cat6a aren't intended for use > beyond 500MHz. While there's less loss because the cable is shorter, it'=
s
> worth looking up the loss curves and doing the calculation. You have > checked that the 'flat' cable does actually contain twisted pairs?
I have opened up a cable now - the pairs are twisted but the turn rate is m= uch lower than what I would have expected - it is about one full turn every= 20cm or so.
> What's the position of the ground with respect to the LVDS pair?
Ground is (only) in this cable, it is paired with RxD: 1st pair: GND + RxD 2nd pair: LVDS 3rd pair: Power + TxD 4th pair: unused
> Is it > adjacent, or further away? Are these direct electrical connections, or i=
s
> there any signal isolation?
Ground is only connected through the cable between the board. The transmitt= er side (a small sensor board) has no other connections to it at all. The r= eceiver side has other connections like HDMI, etc. In fact, there is a ferrite bead on the sensor PCB in the ground and in the= power path (directly at the connector). But I also have already bridged th= is beads with zero ohm -> no change.
> Is the spare pair floating?
Yes. I have removed this wires from one bad cable now -> no change.
> What's the grounding arrangements of both boards? Is this the only groun=
d
> connection between them?=20
See above
> How are they powered? Do they come from the same > AC source, or different sources? What's the arrangement of earths, and a=
ny
> possibility they could be on different AC phases?
The receiving board is powered via an external +12V power supply, the senso= r board is only powered via this cable.
> What are you driving the RXD/TXD signals with? Do you know their rise ti=
me? With 3.3V FPGA I/O pins with series resistors and even some small cap at th= e connector. The rise-time is very slow. I have also stopped the UART commu= nciaton for testing -> no change.
> For that matter, do you know the rise time of the LVDS signals?
Unfortunately: No (I have only a 500 MHz scope)
> What are you using for an LVDS receiver? (Any equalisation?)
It is a Cyclone IVGX SerDes. Yes, equalization is active (at a medium setti= ng). I will play around a little bit with this settings (unfortunately the = compile-time is quite long).
> What's the encoding on the wire (8b/10b, Manchester, etc)?
It is quite a simple protocol with start- and stop-bit (10b data-word) as u= sed by DS92LV1023 (no DC balancing)
> > I tried changing and even removing the termination resistors, this did =
not
> > change the behavior at all. I have changed both boards, it is really t=
he
> > cable that makes the difference. > Have you looked at the signal on a scope?
Yes (as good as possible with a 500MHz scope...): I see no visible change i= n all the signals when touching the cable. Only the dramatic effect in the = error rate. What surprises me is that the scope probe has almost no influen= ce on the error rate while the touching by hand does...
> Where did the 'termination resistors' come from? How did you decide what > topology and what values to use?
They are 100R on both sides (as this is what I expect as impedance of a CAT= 5e cable). I put a 100R also on the transmitter side as this improves the r= obustness in my experience, esp. with longer cables. I also removed the 100= R on the transmitter side and it did not help.
> > Has anybody an idea what the reason of this behavior could be? > Some ideas: > 1. You're changing the capacitance of the cable by touching it > 2. You're creating a capacitive path to ground through your body > 3. You're changing the topology of the inductive loop between an LVDS lin=
e
> and ground > 4. You're coupling other signals into the LVDS pair (eg RXD), especially =
if
> the twists have ended up aligned > 5. The signal has higher frequency components than you think and these ar=
e
> messing up the receiver. Extra capacitance by touching increases their > loss, enough for the receiver to cope > 6. The cable is simply too lossy at the frequency you're using > 7. You have a grounding issue with the setup > 8. The line isn't terminated correctly so you're getting reflections whic=
h
> interfere with the signal
I will have to think further about these...
> Do you have a network analyser available? Looking at the insertion loss =
of
> the cable over a range of frequencies may tell you something about what's > going on.
Unfortunately: No.
> I've done a lot of work with SATA cables. Bottom line is, some are just > cheap and simply don't work. SATA error recovery is enough to mask many =
of
> the problems when used in a PC, so nobody notices. >=20 > Theo
Thanks a lot. This discussing this issue with someone really helps. I will = post new results here when I have any. Regards, Thomas
> > What are you using for an LVDS receiver? (Any equalisation?) > It is a Cyclone IVGX SerDes. Yes, equalization is active (at a medium > setting). > I will play around a little bit with this settings (unfortunately > the compile-time is quite long).
It turned out that the equalization was too high. When increasing the setting, things got worse. When setting it to "low", things work perfect without any errors... I think the great effects of touching the cable can be explained with the weak twisting of the pairs. Regards, Thomas
thomas.entner99@gmail.com wrote:
> It turned out that the equalization was too high. When increasing the > setting, things got worse. When setting it to "low", things work perfect > without any errors... > > I think the great effects of touching the cable can be explained with the > weak twisting of the pairs.
I suspect the cable looks more like a parallel ribbon cable than twisted pair. That means there could be other signals between the twisted pair and ground - eg if it turns out it goes: GND RXD D+ D- TXD VCC Any common mode currents, which there will be because your coding scheme is not DC balanced, will flow around a loop with RXD or TXD in the middle, so are likely to be inductively coupled with these wires (ie cause crosstalk). It's difficult to say what effect the inductance of this loop will have on the LVDS signal (I suspect not a huge amount, but have no numbers: it will depend on how quick the rise times are), but I wouldn't be surprised if you saw coupling into the RXD and TXD wires. Likewise, we'd have to know a bit more about the channel characteristics to predict what the likely frequency response of the channel might be (you'd model each part's LCR properties separately: hard numbers needed). I'd guess that the touching effect increases both the capacitance to ground and the inter-pair capacitance. It moves the frequency nulls around - I'm not familiar with the equalisation settings on that transceiver to know the effect of the different modes, but it's not implausible that equalisation could cope with one but not the other. In theory your transmission line should be correctly terminated so you don't need equalisation, but it very obviously isn't. Theo
thomas.entner99@gmail.com wrote:
> I have an LVDS related issue that drives me crazy:
> There are two boards with a FPGA that are connected by a ca. > 30cm cable. Only 6 wirea are used: > GND + Power > LVDS (with embedded clock), 720Mbps > UART (Rxd + Txd) > (The cable is unshielded for flexibility reasons)
> The cable is a "flat Ethernet cable" with 4 twisted pairs, > one pair is unused, one pair is LVDS, one pair is GND + Rxd > and the last is Power + TxD.
Ethernet cables use pin pairs (1,2) (3,6) (4,5) and (7,8). With the usual cables, you can see the pairs, including the colors, in the connector. I have one, though, which I would call flat, and which the pairs are not visible. It is very thin and flexible, and seems to work fine for 100baseTX. I suspect the wire is much smaller than the normal Cat 5 wire. But otherwise, ethernet cables are normally rated to 100MHz. 1000baseT uses a complicated signal system on all four pairs (in both directions at the same time) to get the bits through. I wouldn't be surprised if you could get 720MHz through Cat 5 cable for 30cm, but your cable might not be quite that good. -- glen
thomas.entner99@gmail.com wrote:


> The cable is a "flat Ethernet cable" with 4 twisted pairs, one pair is > unused, one pair is LVDS, one pair is GND + Rxd and the last is Power + > TxD.
This is NOT LVDS! The D stands for Differential! You use one wire of the pair for the true signal, one wire for the complement signal. I don't even know how you do single-ended with LVDS receivers, but it won't work well, as you clearly have discovered. You can still use LVDS the right way with 3 pairs. One pair is power & ground, one is the Rxd true/compl pair, the other is the Txd true/compl pair. Jon
Den onsdag den 13. august 2014 23.02.24 UTC+2 skrev Jon Elson:
> thomas.entner99@gmail.com wrote: > > > > > > > The cable is a "flat Ethernet cable" with 4 twisted pairs, one pair is > > > unused, one pair is LVDS, one pair is GND + Rxd and the last is Power + > > > TxD. > > This is NOT LVDS! The D stands for Differential! You use one wire of the > > pair for the true signal, one wire for the complement signal. I don't even > > know how you do single-ended with LVDS receivers, but it won't work well, > > as you clearly have discovered. > > > > You can still use LVDS the right way with 3 pairs. One pair is power & > > ground, one is the Rxd true/compl pair, the other is the Txd true/compl > > pair. >
afaiu, he is using one pair for LDVS, the other rx/tx is single ended uart paired with gnd and power. So the wiring is ok -Lasse
Jon Elson <jmelson@wustl.edu> wrote:
> This is NOT LVDS! The D stands for Differential! You use one wire of the > pair for the true signal, one wire for the complement signal. I don't even > know how you do single-ended with LVDS receivers, but it won't work well, > as you clearly have discovered. > > You can still use LVDS the right way with 3 pairs. One pair is power & > ground, one is the Rxd true/compl pair, the other is the Txd true/compl > pair.
The OP stated he has one LVDS pair (D+ and D- twisted), and two UART signals (RXD and TXD). The UART signals aren't sent by LVDS, they're just other things down the same cable. I assume the OP's LVDS is unidirectional (or else there would be other issues). The OP's situation of having RXD+GND and TXD+VCC pairs, rather than RXD+TXD and GND+VCC, is probably slightly better but it's marginal at typical UART speeds (and as always depends on the setup - as we've discovered the 'twisted pair' isn't). You can connect single-ended into an LVDS receiver by grounding the negative input (if you have positive and negative voltage rails) or putting it mid-range via a resistive divider (on a single supply arrangement) but you've just halved your signal amplitude (and thus differential SNR) - and of course you have no protection from common-mode noise. Theo
Theo Markettos wrote:


> The OP stated he has one LVDS pair (D+ and D- twisted), and two UART > signals > (RXD and TXD). The UART signals aren't sent by LVDS, they're just other > things down the same cable.
OK, he confused me with the UART data signals. Well, one other thing, is he terminating the LVDS with a resistor matching the characteristic impedance of the cable? I'll bet he isn't, his results would VERY likely match what he describes. We use 100 Ohm resistors, they are close enough. For best results, tune between 110 and 120 Ohms for minimum reflection. Jon