looking for systemC/TLM 2.0 courses

Hi everyone,

I apologize if this is maybe not the best audience for these kind of 
enquiries but I'll try anyhow.

I'm looking for a good SystemC/TLM 2.0 training course which is not too 
basic and can give me a head start for a real life project.

I'm not a black belt on C++ but I'm familiar with most of its concepts 
on top of C (which I use quite often instead). Since we have a budget 
for training in our company I'd like to make something useful out of it 
and given the current issues we are facing in architecting systems of 
increasingly complex features set, I believe that modeling would add 
value to our products and avoid many issues due to a wrong architecture.

Any ideas/suggestions?

p.s.: I've no problems to start some reading/testing by myself in order 
to fill the gap before attending the course.

-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

alb <al.basili@gmail.com> wrote:
 
> I apologize if this is maybe not the best audience for these kind of 
> enquiries but I'll try anyhow.
 
> I'm looking for a good SystemC/TLM 2.0 training course which is not too 
> basic and can give me a head start for a real life project.

I know it isn't what you asked for, and it is my personal opinion, 
but I recommend that you learn and use Verilog or VHDL instead.
 
> I'm not a black belt on C++ but I'm familiar with most of its concepts 
> on top of C (which I use quite often instead). 

This is the reason why. Hardware design is different from software.

OK, when I started with Verilog some years ago now, it was suggested
that for someone used to C, Verilog was a better choice than VHDL.
Verilog has enough similarity to C to make it easy to learn, but
not so much that you forget that you are designing hardware.

You should be able to think in terms of wires and gates, even when
writing continuous assignment statements and logic expressions.

You should be able to look at a logic schematic diagram and write
HDL statements from it. You should not think in terms of sequential
logic and C programs.

> Since we have a budget 
> for training in our company I'd like to make something useful out of it 
> and given the current issues we are facing in architecting systems of 
> increasingly complex features set, I believe that modeling would add 
> value to our products and avoid many issues due to a wrong architecture.

I don't have any actual recommendations for training courses in any
HDL, but I am sure that they exist for Verilog and VHDL.

-- glen

Hi Glen,

glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote:
[]
> I know it isn't what you asked for, and it is my personal opinion, 
> but I recommend that you learn and use Verilog or VHDL instead.

I use VHDL since more than 10 years and even though I agree that 
learning to use it more efficiently is good, unfortunately is not top 
priority for the time being.
 
>> I'm not a black belt on C++ but I'm familiar with most of its concepts 
>> on top of C (which I use quite often instead). 
> 
> This is the reason why. Hardware design is different from software.

I do not want to do hardware design. I want to explore the type of 
architecture in order to give the go to the designers. On top of that an 
architecture may have several parameters (bus bandwidth, latencies, I/O 
throughput, etc.), therefore it is important to see 'easily' what is the 
impact on the architecture if we need to increase a value from A to B, 
will the overall design fall apart? Will the bandwidth be not 
sufficient, will it require too much memory?

I've learned to simulate my vhdl designs thinking in terms of 
transactions and I believe I can 'model' my system in behavioral vhdl, 
but I'm not sure is the most efficient way. We have embedded processors 
for which a behavioral model would be hard to replicate, while several 
of them are available in SystemC.

IMHO a modeling phase should not give the impression that we can 
generate the vhdl from the said model. The main idea is to verify that 
we are not going against a wall during the implementation phase because 
we didn't have enough margins.

A functional model should not have the low level details, but the 
transaction should be representative of the amount of data flow 
foreseen. A simple example would be the amount of traffic on the on 
board bus, every transfer should consider the amount of time it takes 
for the handshake on the bus, with timing values that match with the 
intended platform.

Ideally then, the model may cover more than just the FPGA functions and 
go up to board level and system level (more boards together). I couldn't 
care less if the board has all the necessary buffers to handle the speed 
we want, on the contrary I need to see, given a specified throughput 
what is the optimal bus size (8/16/32/64...). Power considerations may 
need to be added as well.

> 
> OK, when I started with Verilog some years ago now, it was suggested
> that for someone used to C, Verilog was a better choice than VHDL.
> Verilog has enough similarity to C to make it easy to learn, but
> not so much that you forget that you are designing hardware.

I believe learning verilog is too low in my priority list... (and will 
soon fall off the list!).

> You should be able to think in terms of wires and gates, even when
> writing continuous assignment statements and logic expressions.

I want to get out of the wires and gates level. At least for the phase 
I'm interested in. /Polluting/ the architecturing phase with such level of 
details is risky and will inevitably blur the big picture.

[]
> I don't have any actual recommendations for training courses in any
> HDL, but I am sure that they exist for Verilog and VHDL.

I know already a couple of courses for VHDL that I'm interested in, but 
unfortunately they are not in my current priority list (but they are 
still in the list!).

Al

Hi Al,
On 09/10/2014 07:58, alb wrote:
> Hi everyone,
>
> I apologize if this is maybe not the best audience for these kind of
> enquiries but I'll try anyhow.
>
> I'm looking for a good SystemC/TLM 2.0 training course which is not too
> basic and can give me a head start for a real life project.
>
> I'm not a black belt on C++ but I'm familiar with most of its concepts
> on top of C (which I use quite often instead). Since we have a budget
> for training in our company I'd like to make something useful out of it
> and given the current issues we are facing in architecting systems of
> increasingly complex features set, I believe that modeling would add
> value to our products and avoid many issues due to a wrong architecture.
>
> Any ideas/suggestions?

I would definitely recommend the Doulos course, I have done their 
Comprehensive SystemC one and it was very good. The only disappointment 
was that we ran out of time so SCV, TLM and Synthesis were not properly 
looked at.

Good luck,
Hans
www.ht-lab.com


>
> p.s.: I've no problems to start some reading/testing by myself in order
> to fill the gap before attending the course.
>

Hi Hans,

HT-Lab <hans64@htminuslab.com> wrote:
[]
>> I'm looking for a good SystemC/TLM 2.0 training course which is not too
>> basic and can give me a head start for a real life project.
[]

> I would definitely recommend the Doulos course, I have done their 
> Comprehensive SystemC one and it was very good. The only disappointment 
> was that we ran out of time so SCV, TLM and Synthesis were not properly 
> looked at.

I hoped you chimed in and knowing you recommend that course is a big 
reassurance. We are not so much interested in SCV or Synthesis but we 
are definitely interested in TLM.

There's a possibility that more people are interested in our site and we 
suddenly break through the right number to have them on site. I believe 
if that happens we can have a much more tailored course based on our 
needs and background.

Al

Hi alb,

if I may ask; where (which country) are you located? Have you ever attended another Doulos seminar? What is your experience? Especially with respect to UVM.

> Hi Hans,

Hi Hans! Hope you are doing well.

Best regards
Nikolaos Kavvadias
http://www.nkavvadias.com
http://github.com/nkkav/elemapprox

Hi Nikolaos,

Nikolaos Kavvadias <nikolaos.kavvadias@gmail.com> wrote:
> if I may ask; where (which country) are you located? Have you ever 
> attended another Doulos seminar? What is your experience? Especially 
> with respect to UVM.

I've followed several webinars but never a course. If I ever manage to 
convince my managers to send me to their courses I'll post a review, no 
worries! I live in Switzerland.

Al

On 09/10/2014 13:04, Nikolaos Kavvadias wrote:
> Hi alb,
>
> if I may ask; where (which country) are you located? Have you ever attended another Doulos seminar? What is your experience? Especially with respect to UVM.
>
Like Al, I also watch some seminars/webex' on the UVM and it gave me a 
headache so this is clearly something a 5 day training course would be 
ideal for.

>> Hi Hans,
>
> Hi Hans! Hope you are doing well.

Hi Nikolaos,

Yes thanks, I spend another great 2 weeks on one of your islands 
(Poros). Anybody who is fed up fighting FPGA, PCB, EDA tools I would 
highly recommend a quiet Greek island for a few weeks ;-)

Regards,
Hans.
www.ht-lab.com


>
> Best regards
> Nikolaos Kavvadias
> http://www.nkavvadias.com
> http://github.com/nkkav/elemapprox
>

Dear Hans,

> Hi Nikolaos,
>=20
> Yes thanks, I spend another great 2 weeks on one of your islands=20
> (Poros).=20

Great! My brothers visited near-by sites this year: Hydra, Spetses (islands=
) and Nafplion (mainland). Hydra and Spetses are quite close to Poros (clos=
est islands anyway). Historically speaking these tiny islands played a majo=
r part in the Greek Independence War (1821-1828).

I don't know much details; this band of brothers rarely meets in its entire=
ty these days: maybe once a year or every two years or so.

> Anybody who is fed up fighting FPGA, PCB, EDA tools I would=20
> highly recommend a quiet Greek island for a few weeks ;-)

Nothing to add here ^_--

Best regards
Nikolaos Kavvadias
http://www.nkavvadias.com
=20
> Regards,
> Hans.
>=20
> www.ht-lab.com
>=20
>=20
>=20
>=20
>=20
> >
>=20
> > Best regards
>=20
> > Nikolaos Kavvadias
>=20
> > http://www.nkavvadias.com
>=20
> > http://github.com/nkkav/elemapprox
>=20
> >

On 09/10/14 11:16, alb wrote:
> Hi Hans,
> 
> HT-Lab <hans64@htminuslab.com> wrote:
> []
>>> I'm looking for a good SystemC/TLM 2.0 training course which is not too
>>> basic and can give me a head start for a real life project.
> []
> 
>> I would definitely recommend the Doulos course, I have done their 
>> Comprehensive SystemC one and it was very good. The only disappointment 
>> was that we ran out of time so SCV, TLM and Synthesis were not properly 
>> looked at.
> 
> I hoped you chimed in and knowing you recommend that course is a big 
> reassurance. We are not so much interested in SCV or Synthesis but we 
> are definitely interested in TLM.
> 
> There's a possibility that more people are interested in our site and we 
> suddenly break through the right number to have them on site. I believe 
> if that happens we can have a much more tailored course based on our 
> needs and background.
> 
> Al
> 

I used to work for Doulos, and teach SystemC and TML2 - we regularly ran
courses at CERN, but normally VHDL and some Expert VHDL. Something makes
me think you're based at CERN.

Since Hans did the course, the SCV content was relegated to an appendix.
The main SystemC course included an introduction to TLM2, then there was
a separate TLM2 course.

Knowing C++ is a definite advantage!

Have a look at the Doulos website, or email info@doulos.com,

regards
Alan

-- 
Alan Fitch