Hi Alan, Alan Fitch <apf@invalid.invalid> wrote:> I used to work for Doulos, and teach SystemC and TML2 - we regularly ran > courses at CERN, but normally VHDL and some Expert VHDL. Something makes > me think you're based at CERN.I used to, has been a fun ride. Too bad I never got the chance to follow a course of yours. It seems now they are more and more pushing for SystemVerilog, while I lately was trying to fight my way with OSVVM which I find more appropriate for that type of community.> Knowing C++ is a definite advantage!Uhm, 'knowing' is actually a bit vague, considering that I strongly believe that in order to 'know' a language it takes ~10 years of practice in the field! (I actually find this reading quite at the point: http://norvig.com/21-days.html)> Have a look at the Doulos website, or email info@doulos.com,I did. BTW I found that A.L.S.E. (http://www.alse-fr.com/about.php) provides the very same course from Doulos, are the instructors coming from Doulos or they are simply acting as a gateaway to Doulos courses? Al
looking for systemC/TLM 2.0 courses
Started by ●October 9, 2014
Reply by ●October 11, 20142014-10-11
Reply by ●October 12, 20142014-10-12
On 11/10/14 15:27, alb wrote:> Hi Alan, > > Alan Fitch <apf@invalid.invalid> wrote: >> I used to work for Doulos, and teach SystemC and TML2 - we regularly ran >> courses at CERN, but normally VHDL and some Expert VHDL. Something makes >> me think you're based at CERN. > > I used to, has been a fun ride. Too bad I never got the chance to follow > a course of yours. It seems now they are more and more pushing for > SystemVerilog, while I lately was trying to fight my way with OSVVM > which I find more appropriate for that type of community. >I'm afraid it's "the dead hand of the market"...>> Knowing C++ is a definite advantage! > > Uhm, 'knowing' is actually a bit vague, considering that I strongly > believe that in order to 'know' a language it takes ~10 years of > practice in the field! (I actually find this reading quite at the point: > http://norvig.com/21-days.html) >People who know C++ well, and who have some experience of VHDL or Verilog generally get on well with SystemC as "it's just another class library". If you know VHDL/Verilog but don't know any object orientated language it can be "challenging" :-) However knowing Java (for instance) doesn't mean you know C++ of course (though can be quite helpful when learning SystemVerilog!). The Doulos Comprehensive SystemC includes 2 days of C++ at the beginning, aimed at people who know C but not C++. For on-site training the courses can be customised - but trying to compress the equivalent of 2 days C++ + 2 days SystemC + 3 days TLM2 can lead to peoples' brains metaphorically exploding.>> Have a look at the Doulos website, or email info@doulos.com, > > I did. BTW I found that A.L.S.E. (http://www.alse-fr.com/about.php) > provides the very same course from Doulos, are the instructors coming > from Doulos or they are simply acting as a gateaway to Doulos courses? >ALSE have their own instructors. I remember they had one person up-to-scratch with SystemC. Generally they ran the courses in French. They use the same Doulos materials. regards Alan -- Alan Fitch
Reply by ●October 13, 20142014-10-13
Hi Alan,> > I used to, has been a fun ride. Too bad I never got the chance to follow > > > a course of yours. It seems now they are more and more pushing for > > > SystemVerilog, while I lately was trying to fight my way with OSVVM > > > which I find more appropriate for that type of community. > > > > > > > I'm afraid it's "the dead hand of the market"...Perhaps a shrinking market for Doulos, however, it has been a growing market for us (including in UK). What I do see in SystemVerilog's favor is the vendors are pushing the user community heavily to it since they can make more money with SystemVerilog licenses. OTOH, recently we have had people switching from SystemVerilog to VHDL/OSVVM because their projects could not afford the pricing of a SystemVerilog simulator when OSVVM can do the same thing. Cheers, Jim
Reply by ●October 14, 20142014-10-14
Hi Jim, Jim Lewis <usevhdl@gmail.com> wrote: []> What I do see in SystemVerilog's favor is the vendors are pushing the > user community heavily to it since they can make more money with > SystemVerilog licenses.This is one of our concerns as well. While the OSVVM seems covering the needs in terms of functionality, it still lacks the support needed in terms of verification IPs which may be a big plus (or minus). Do you see anything coming soon on that side of the market or people using OSVVM will be forced to develop their own verification IPs?> OTOH, recently we have had people switching from SystemVerilog to > VHDL/OSVVM because their projects could not afford the pricing of a > SystemVerilog simulator when OSVVM can do the same thing.Same here. Management won't provide the necessary means to go buying licenses for SV simulators and on top of that most of our team is hardware oriented. We actually proposed several training courses on OSVVM for next year budget hoping to get at least a couple (and I'm not included!). Al
Reply by ●October 17, 20142014-10-17
On 13/10/14 18:35, Jim Lewis wrote:> Hi Alan, >>> I used to, has been a fun ride. Too bad I never got the chance to follow >> >>> a course of yours. It seems now they are more and more pushing for >> >>> SystemVerilog, while I lately was trying to fight my way with OSVVM >> >>> which I find more appropriate for that type of community. >> >>> >> >> >> >> I'm afraid it's "the dead hand of the market"... > > Perhaps a shrinking market for Doulos, however, it has been a growing market for us (including in UK). > > What I do see in SystemVerilog's favor is the vendors are pushing the user community heavily to it since they can make more money with SystemVerilog licenses. > > OTOH, recently we have had people switching from SystemVerilog to VHDL/OSVVM because their projects could not afford the pricing of a SystemVerilog simulator when OSVVM can do the same thing. > > Cheers, > Jim > > >I just want to clarify that I left Doulos a year ago, and I have no knowledge of their current market. Also I didn't say that the VHDL market is shrinking. What I was trying to say is that there's more demand for SystemVerilog training than VHDL - but that doesn't mean that VHDL is necessarily shrinking. regards Alan -- Alan Fitch
Reply by ●October 18, 20142014-10-18
On 18/10/2014 00:37, Alan Fitch wrote: Hi Alan, ..> > I just want to clarify that I left Doulos a year ago, and I have no > knowledge of their current market. Also I didn't say that the VHDL > market is shrinking.I guess using "the dead hand of the market" is not the most appropriate phrase for the leading FPGA design language.> What I was trying to say is that there's more > demand for SystemVerilog training than VHDL -I am not sure that is correct from what I understand VHDL is still the most popular Doulos language course, also if you look at the current schedule there are more VHDL than SystemVerilog courses.> but that doesn't mean that > VHDL is necessarily shrinking.I agree with Jim that the EDA industry seems to be doing its best to make this happen ;-) Hope you are enjoying your new job and are allowed to use VHDL and SystemC, Regards, Hans. www.ht-lab.com> > regards > > Alan >
