ISE 14.6 and picoblaze synthesis problem (translate_on/off directives ignored ?)

Hello
I am trying to implement a design containing a picoBlaze (source code I hav=
e already used numerous times) in a new project with ISE 14.6, and synthesi=
s chokes on the numerous INIT parameters that are encased in translate_off/=
translate_on directives and should therefore be ignored.
Has the directives support changed since previous versions ? Is there some =
setting I should have set when creating the project ?

Nicolas

nmatringe@gmail.com wrote:
> Hello
> I am trying to implement a design containing a picoBlaze (source code I have already used numerous times) in a new project with ISE 14.6, and synthesis chokes on the numerous INIT parameters that are encased in translate_off/translate_on directives and should therefore be ignored.
> Has the directives support changed since previous versions ? Is there some setting I should have set when creating the project ?
> 
> Nicolas

Some older sources use "synopsis translate_on/_off" rather than
"synthesis translate_on/_off" syntax.  If this is the problem
in PicoBlaze, the synopsis syntax may have been deprecated.

-- 
Gabor

Le lundi 13 octobre 2014 22:56:24 UTC+2, Gabor a =E9crit=A0:
> nmatringe@gmail.com wrote:
>> I am trying to implement a design containing a picoBlaze (source code I =
have already used numerous times) in a new project with ISE 14.6, and synth=
esis chokes on the numerous INIT parameters that are encased in translate_o=
ff/translate_on directives and should therefore be ignored.
>=20
> Some older sources use "synopsis translate_on/_off" rather than
> "synthesis translate_on/_off" syntax.  If this is the problem
> in PicoBlaze, the synopsis syntax may have been deprecated.

It seems to me that the documentation mentions "synopsis" as a valid direct=
ive, unless I read an old version. Anyway the source actually uses "synthes=
is" as a key word.

What puzzles me the most is that older projects using the exact same pB sou=
rce (I diffed the files) imported into 14.6 implement just fine.

Nicolas

Le mardi 14 octobre 2014 10:23:30 UTC+2, nmat...@gmail.com a =E9crit=A0:

> What puzzles me the most is that older projects using the exact same pB s=
ource (I diffed the files) imported into 14.6 implement just fine.

The problem is actually with attributes, not with the generic parameters an=
d synthesis directives.
I'm still puzzled older design work...

An example of error message I get:
ERROR:Xst:3154 - "C:\Users\nmatring\Documents\NGC_sniffer\FPGA\src\kcpsm3.v=
hd". Line 289. Unable to set attribute "INIT" with value "1" on instance <t=
_state_lut> of block <LUT1>. This property is already defined with value "0=
" on the block definition by a VHDL generic or a Verilog parameter. Apply t=
he desired value by overriding the default VHDL generic or Verilog paramete=
r. Using an attribute is not allowed.

Nicolas

Silly me...
https://www.google.fr/?gws_rd=ssl#q=xilinx+error+xst+3154

My older projects were targetting Spartan 3 and weren't impacted.
Case closed.

Nicolas

nmatringe@gmail.com wrote:
> Silly me...
> https://www.google.fr/?gws_rd=ssl#q=xilinx+error+xst+3154
> 
> My older projects were targetting Spartan 3 and weren't impacted.
> Case closed.
> 
> Nicolas

You didn't mention the new target device, but I assume it is
6-series or newer?  That's when the "new parser" was introduced.

-- 
Gabor