Due to a calamtity of computer problems, including some affecting my backups, I'm suddenly in desparate need of StateCad Version 4.11 (or possibly Version 5.0) to support an active project. An evaluation version is fine. Can anyone help?
Need StateCAD 4.11!
Started by ●August 4, 2004
Reply by ●August 4, 20042004-08-04
mwm11@cornell.edu (mmock) wrote in message news:<b2c16e8.0408032014.5129bb5c@posting.google.com>...> Due to a calamtity of computer problems, including some affecting my > backups, I'm suddenly in desparate need of StateCad Version 4.11 (or > possibly Version 5.0) to support an active project. An evaluation > version is fine. Can anyone help?eMule is your friend. Check it out and see if you can find a copy there. :)
Reply by ●August 5, 20042004-08-05
As is suprnova, etc. no luck at all... I can't be the only person in the world using StateCAD to generate C code!! sense_1909S_VDB@yahoo.com (google_guy) wrote in message news:<cc4cf599.0408041328.7a6e24cd@posting.google.com>...> mwm11@cornell.edu (mmock) wrote in message news:<b2c16e8.0408032014.5129bb5c@posting.google.com>... > > Due to a calamtity of computer problems, including some affecting my > > backups, I'm suddenly in desparate need of StateCad Version 4.11 (or > > possibly Version 5.0) to support an active project. An evaluation > > version is fine. Can anyone help? > > eMule is your friend. Check it out and see if you can find a copy there. :)
Reply by ●August 5, 20042004-08-05
I don't use it. I tried it or a similar program awhile back and I found that it just put another level of confusion between me and the hardware. I normally like to have better control over the bits in an FPGA. If you read some examples on the web, I am sure you will find it easy to code FSMs directly in VHDL (or verilog). If you email me a GIF or PDF of your state diagram I would be happy to show you how I would code it. mmock wrote:> > As is suprnova, etc. no luck at all... I can't be the only person in > the world using StateCAD to generate C code!! > > sense_1909S_VDB@yahoo.com (google_guy) wrote in message news:<cc4cf599.0408041328.7a6e24cd@posting.google.com>... > > mwm11@cornell.edu (mmock) wrote in message news:<b2c16e8.0408032014.5129bb5c@posting.google.com>... > > > Due to a calamtity of computer problems, including some affecting my > > > backups, I'm suddenly in desparate need of StateCad Version 4.11 (or > > > possibly Version 5.0) to support an active project. An evaluation > > > version is fine. Can anyone help? > > > > eMule is your friend. Check it out and see if you can find a copy there. :)-- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
Reply by ●August 6, 20042004-08-06
Rick--Thanks very much for your offer to help. I hand coded FSM's for years before StateCAD came along. The advantage of StateCAD is accurate visual documentation to support checkout, less room for human error, repeatability when making changes, and productivity. The current project I'm doing has six packed pages with over a hundred states. I'll trade hours of tedious error-prone hand coding for the click of a mouse any day. And the dividends pay out every time I make a significant change. I'm grateful for your offer for help. (BTW, I found that the free Xilinx version of Webpack ISE reads my old Version 4.11 files fine and spits out Verilog, VHDL, and ABEL. I need the C output, however. Evidently Xilinx dropped that.) rickman <spamgoeshere4@yahoo.com> wrote in message news:<4112AB03.EAE7F85B@yahoo.com>...> I don't use it. I tried it or a similar program awhile back and I found > that it just put another level of confusion between me and the > hardware. I normally like to have better control over the bits in an > FPGA. If you read some examples on the web, I am sure you will find it > easy to code FSMs directly in VHDL (or verilog). If you email me a GIF > or PDF of your state diagram I would be happy to show you how I would > code it. > > > mmock wrote: > > > > As is suprnova, etc. no luck at all... I can't be the only person in > > the world using StateCAD to generate C code!! > > > > sense_1909S_VDB@yahoo.com (google_guy) wrote in message news:<cc4cf599.0408041328.7a6e24cd@posting.google.com>... > > > mwm11@cornell.edu (mmock) wrote in message news:<b2c16e8.0408032014.5129bb5c@posting.google.com>... > > > > Due to a calamtity of computer problems, including some affecting my > > > > backups, I'm suddenly in desparate need of StateCad Version 4.11 (or > > > > possibly Version 5.0) to support an active project. An evaluation > > > > version is fine. Can anyone help? > > > > > > eMule is your friend. Check it out and see if you can find a copy there. :) > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX
Reply by ●August 6, 20042004-08-06
mwm11@cornell.edu (mmock) wrote in message news:<b2c16e8.0408051935.4b2c1d96@posting.google.com>...> Rick--Thanks very much for your offer to help. I hand coded FSM's for > years before StateCAD came along. The advantage of StateCAD is > accurate visual documentation to support checkout, less room for human > error, repeatability when making changes, and productivity.I might buy that if simulation were not available, but I have to agree with Rick. Consider coding in text, writing a standard testbench and thus eliminate the dependence on an obsolete tool.> The > current project I'm doing has six packed pages with over a hundred > states. I'll trade hours of tedious error-prone hand coding for the > click of a mouse any day.Six pages of circles and arrows might fit on one page of code and comments.> (BTW, I found that the free Xilinx version of Webpack ISE reads my old > Version 4.11 files fine and spits out Verilog, VHDL, and ABEL. I need > the C output, however. Evidently Xilinx dropped that.)Do you have the generated C code from the previous revision? What are you doing with C code? Good Luck, -- Mike Treseler
Reply by ●August 8, 20042004-08-08
Mike Treseler wrote:> > mwm11@cornell.edu (mmock) wrote in message news:<b2c16e8.0408051935.4b2c1d96@posting.google.com>... > > > Rick--Thanks very much for your offer to help. I hand coded FSM's for > > years before StateCAD came along. The advantage of StateCAD is > > accurate visual documentation to support checkout, less room for human > > error, repeatability when making changes, and productivity. > > I might buy that if simulation were not available, but > I have to agree with Rick. Consider coding in text, writing > a standard testbench and thus eliminate the > dependence on an obsolete tool.If he does not have speed issues and has a complex state diagram, then I can see his preference for a tool. I personally can code in VHDL and understand my FSM very well. But certainly working from a diagram is very useful. So, to each his own.> > The > > current project I'm doing has six packed pages with over a hundred > > states. I'll trade hours of tedious error-prone hand coding for the > > click of a mouse any day. > > Six pages of circles and arrows might fit on one > page of code and comments.My experience is that the code written for easy understanding is slightly verbose and can be a bit inefficient. To gain the best efficiency, you need to do hand optimizations that can lead to errors. But a non-optimized coding is still likely as good or better than generated code from a tool. But I would still expect it to be at least as many pages or more than the state diagrams. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
Reply by ●August 8, 20042004-08-08
Mike, I don't have a copy of C code for the current project. I have from other projects. It's just a case statement. Switch on current state and inputs. Outputs are a function of next state. Nothing complex. The only complexity is volume, volume of states, volume of inputs and outputs, and volume of decisions. The tool gets them right every time, and at the speed of my cpu. All I need to do is get the diagram correct. Since I am a visual person, this is both easy and enjoyable for me. Yes, the code is occasionally verbose. There are different areas of efficiency. How much memory does the executable take up? How fast does it run? How much production shedule does it take to write and test the code? How much paper does the source code use when you print it out? I like to think that I look at the problem at hand and concentrate on improving efficiency where and when I need it. I get in trouble when my purist side wastes efficiency in one area to obtain efficiency in an area where I don't need it. Some people can hand code, fix all the errors, make changes, and deliver the result very quickly. Some people get bogged down in the tedium and procrastinate unless they have a tool. To each engineer his own. To each problem at hand, it's own best solution. For this project that I'm on right now, the "tool" is the best approach. Simulation is immensely helpful, but again, I simulate against the diagram. Even if I hand-optimize, I still go back and simulate against the diagram. So the tool does only one thing for me, eliminate the tedious step, and it does it exceptionally well. To say that StateCAD is obsolete is to say that C is obsolete, because StateCAD is alive and thriving generating VHDL and Verilog for thousands of people. Xilinx paid LOTS of money to buy this "obsolete" technology and embed it into their tool set to generate VHDL and Verilog. But you're right, they don't generate C. If C is obsolete, then please let me know where I can get a VHDL compiler so I can start using VHDL to program my Motorola DSP56F803 cpu. I didn't intend the thread to be a debate the pros and cons of the tool, but it brings me to answer your second question. I'm putting the C code into the body of my 56F803 code. I write a shell that reads the ADC's/I/O and writes to the outputs. The shell loops continuously around the FSM. Behaviour of the controller is defined by the diagram. Very sweet. Very simple. Only the diagram is very complex. Don't get me wrong, I LOVE a good debate. And I understand the issues on the subject. I hand-coded for years and drew counless diagrams in MacDraw before I made the transition to the "tool." I learned the hard way all the drawbacks of the tool, but also welcomed the automation that eliminated the tedium and human errors of the pre-tool days. For the problem in my lap now, the tool is the way to go. Does anybody know where I can get my hands on a copy of StateCAD 4.11?? Mike Mock> > Do you have the generated C code from the previous revision? > What are you doing with C code? > > Good Luck, > > -- Mike Treseler
Reply by ●September 9, 20042004-09-09
Hi Mike, I was looking for same thing and found 30-day evaluation on: http://www.embeddedtechnology.com/content/Downloads/SoftwareDesc.asp?DocID={1e91e7bc-edee-11d2-94bd-00a0c9b3bdf2}&VNETCOOKIE=NO I had to register first. Good luck, Borut.
Reply by ●September 9, 20042004-09-09
Hi Mike, I was looking for same thing and found 30-day evaluation on: http://www.embeddedtechnology.com/content/Downloads/SoftwareDesc.asp?DocID={1e91e7bc-edee-11d2-94bd-00a0c9b3bdf2}&VNETCOOKIE=NO I had to register first. Good luck, Borut.
