Which Altera to buy?

Greetings. I am new to FPGA programming. I am
seeking to create a 40-bit 80386-like CPU core
with a 32-bit and 64-bit FPU with 16 registers,
a 128-bit four- and two-way 32-bit and 64-bit
vector FPU engine with 16 registers, 60
additional general purpose integer registers,
and a six stage execution pipeline.

I am wondering if somebody can guide me into
which Altera product I should use for this CPU design? Thank you in advance.

Best regards,
Rick C. Hodgin

rick.c.hodgin@gmail.com wrote:

> Greetings. I am new to FPGA programming. I am
> seeking to create a 40-bit 80386-like CPU core
> with a 32-bit and 64-bit FPU with 16 registers,
> a 128-bit four- and two-way 32-bit and 64-bit
> vector FPU engine with 16 registers, 60
> additional general purpose integer registers,
> and a six stage execution pipeline.
 
> I am wondering if somebody can guide me into
> which Altera product I should use for this CPU design? 

Most likely a big one. 

If you simplify the system somewhat, maybe only a medium sized one.

-- glen

On 12/1/2014 11:20 PM, rick.c.hodgin@gmail.com wrote:
> Greetings. I am new to FPGA programming. I am
> seeking to create a 40-bit 80386-like CPU core
> with a 32-bit and 64-bit FPU with 16 registers,
> a 128-bit four- and two-way 32-bit and 64-bit
> vector FPU engine with 16 registers, 60
> additional general purpose integer registers,
> and a six stage execution pipeline.
>
> I am wondering if somebody can guide me into
> which Altera product I should use for this CPU design? Thank you in advance.

There is some interesting software they provide for working with Altera 
FPGAs called Quartus.  It will let you synthesize your designs and 
measure the size.  Then you can tell what size part it will fit.  No 
guesswork required.  :)

The same package has a simulator to allow you to do a lot of testing 
without ever buying a chip or board.

So design your chip, do *lots* of simulating to verify that all the 
instructions work.  Optimize your architecture and then, only then 
consider which chip you need to buy.

You might want to look for one that has hardware floating point support 
since you plan to implement floating point.  But the size words they 
implement may not be the size you want so you may need to do that in the 
fabric anyway.

-- 

Rick

rick.c.hodgin@gmail.com wrote:
> Greetings. I am new to FPGA programming. I am
> seeking to create a 40-bit 80386-like CPU core
> with a 32-bit and 64-bit FPU with 16 registers,
> a 128-bit four- and two-way 32-bit and 64-bit
> vector FPU engine with 16 registers, 60
> additional general purpose integer registers,
> and a six stage execution pipeline.

For a point of comparison, we have a 64-bit MIPS-like CPU core, with MMU,
L1/L2 cache, 32-bit floating point support, capability unit (32x 256-bit
registers), and a 256 bit datapath to DDR2 memory, and it runs at 100MHz in
about 80% of a Stratix IV GX230 (230K LEs).  Picture and numbers on page 10
here (the Stratix IV doesn't have hard floating point):
http://www.cl.cam.ac.uk/research/security/ctsrd/pdfs/201406-isca2014-cheri.pdf

This is not particularly optimised for size (or speed), and when you put
more things on the FPGA the area usage for the CPU shrinks as the tools work
harder.  We're trying to make it fit in a Cyclone V SoC part
(5CSXFC6D6F31C6N) but haven't yet trimmed it down sufficiently.

The 10 family apparently supports hard floating point: the Stratix 10 is not
available yet but the Arria 10 might be worth a look.

The Arria family is also worth looking at from a cost per LE point of view:
according to my graph on page 2 here:
http://www.cl.cam.ac.uk/~atm26/pubs/FPL2014-ClusterInterconnect.pdf
it works out somewhat cheaper LUT-for-LUT than the Stratix parts.

Theo

On 12/2/2014 6:51 AM, Theo Markettos wrote:
> rick.c.hodgin@gmail.com wrote:
>> Greetings. I am new to FPGA programming. I am
>> seeking to create a 40-bit 80386-like CPU core
>> with a 32-bit and 64-bit FPU with 16 registers,
>> a 128-bit four- and two-way 32-bit and 64-bit
>> vector FPU engine with 16 registers, 60
>> additional general purpose integer registers,
>> and a six stage execution pipeline.
>
> For a point of comparison, we have a 64-bit MIPS-like CPU core, with MMU,
> L1/L2 cache, 32-bit floating point support, capability unit (32x 256-bit
> registers), and a 256 bit datapath to DDR2 memory, and it runs at 100MHz in
> about 80% of a Stratix IV GX230 (230K LEs).  Picture and numbers on page 10
> here (the Stratix IV doesn't have hard floating point):
> http://www.cl.cam.ac.uk/research/security/ctsrd/pdfs/201406-isca2014-cheri.pdf
>
> This is not particularly optimised for size (or speed), and when you put
> more things on the FPGA the area usage for the CPU shrinks as the tools work
> harder.  We're trying to make it fit in a Cyclone V SoC part
> (5CSXFC6D6F31C6N) but haven't yet trimmed it down sufficiently.
>
> The 10 family apparently supports hard floating point: the Stratix 10 is not
> available yet but the Arria 10 might be worth a look.
>
> The Arria family is also worth looking at from a cost per LE point of view:
> according to my graph on page 2 here:
> http://www.cl.cam.ac.uk/~atm26/pubs/FPL2014-ClusterInterconnect.pdf
> it works out somewhat cheaper LUT-for-LUT than the Stratix parts.

Nice info.  You might consider using a log scale for the pricing axis. 
That would help spread out the low end rather than having all that data 
bunched into the corner.  Maybe even log the size axis too.

-- 

Rick

Thank you for the replies and info.

I will be designing my CPU in several stages. I
have the first stage designed but not debugged.
Am working on that this week (Lord willing).

Would it be preferable to design and test each
in Quartus-II only? What about DRAM controllers?
And Ethernet? I plan on using Ethernet for remote
debugging during development and testing. And
do I want a dev board with VGA out to make it
easier? Or should I pass everything through the
Ethernet port?

Thank you in advance for your assistance. It is
greatly appreciated. :-)

Best regards,
Rick C. Hodgin

On 12/2/2014 7:58 AM, rick.c.hodgin@gmail.com wrote:
> Thank you for the replies and info.
>
> I will be designing my CPU in several stages. I
> have the first stage designed but not debugged.
> Am working on that this week (Lord willing).
>
> Would it be preferable to design and test each
> in Quartus-II only? What about DRAM controllers?
> And Ethernet? I plan on using Ethernet for remote
> debugging during development and testing. And
> do I want a dev board with VGA out to make it
> easier? Or should I pass everything through the
> Ethernet port?

I'm not sure what would be easier.  I've never worked with Ethernet in 
an FPGA before.  I would think you could get a VGA interface working 
faster than an Ethernet interface will all the software required.  Are 
you planning to run Linux on it or will you be coding to the bare metal 
without an OS?  Will your Ethernet interface be a full custom or are you 
going to use an Ethernet module that provides a serial link to your CPU?

-- 

Rick

On Tuesday, December 2, 2014 8:13:23 AM UTC-5, rickman wrote:
> On 12/2/2014 7:58 AM, rick.c.hodgin@gmail.com wrote:
> > Thank you for the replies and info.
> >
> > I will be designing my CPU in several stages. I
> > have the first stage designed but not debugged.
> > Am working on that this week (Lord willing).
> >
> > Would it be preferable to design and test each
> > in Quartus-II only? What about DRAM controllers?
> > And Ethernet? I plan on using Ethernet for remote
> > debugging during development and testing. And
> > do I want a dev board with VGA out to make it
> > easier? Or should I pass everything through the
> > Ethernet port?
> 
> I'm not sure what would be easier.  I've never worked with Ethernet in 
> an FPGA before.  I would think you could get a VGA interface working 
> faster than an Ethernet interface will all the software required.  Are 
> you planning to run Linux on it or will you be coding to the bare metal 
> without an OS?  Will your Ethernet interface be a full custom or are you 
> going to use an Ethernet module that provides a serial link to your CPU?

I found a simple Ethernet controller on fpga4fun:

    http://www.fpga4fun.com/10BASE-T.html

I plan on creating a simple buffer which receives internal pipe stage
information at each CPU clock, and then transmits that data back out in
real-time to some a port being monitored by my debugger.  This will allow
me to then constantly monitor the machine state.  I can also then encode
external source level single-step debugging, assembly tools, make even
program changes in real-time, etc., to complete the entire toolset.

I developed my own kernel and primitive OS back in the late 90s, early
00s.  I will be using a modified version of that as the ISA I'm using
is somewhat different than the actual 80386 ISA in (except in
compatibility mode, which I will probably add last).

I'm thinking I would also like to figure out and test timing on a fixed
SVGA video mode for a 1920x1080 signal at 60 Hz, and just hard-code that
video mode and use it for everything the machine does until I can later
add other modes.  And the same for a DRAM controller so I can have that
consistent and normal access to memory, Ethernet, and VGA throughout all
of my development.

Best regards,
Rick C. Hodgin

On Tuesday, December 2, 2014 8:36:34 AM UTC-5, Rick C. Hodgin wrote:
> On Tuesday, December 2, 2014 8:13:23 AM UTC-5, rickman wrote:
> > On 12/2/2014 7:58 AM, rick.c.hodgin@gmail.com wrote:
> > > Thank you for the replies and info.
> > >
> > > I will be designing my CPU in several stages. I
> > > have the first stage designed but not debugged.
> > > Am working on that this week (Lord willing).
> > >
> > > Would it be preferable to design and test each
> > > in Quartus-II only? What about DRAM controllers?
> > > And Ethernet? I plan on using Ethernet for remote
> > > debugging during development and testing. And
> > > do I want a dev board with VGA out to make it
> > > easier? Or should I pass everything through the
> > > Ethernet port?
> > 
> > I'm not sure what would be easier.  I've never worked with Ethernet in 
> > an FPGA before.  I would think you could get a VGA interface working 
> > faster than an Ethernet interface will all the software required.  Are 
> > you planning to run Linux on it or will you be coding to the bare metal 
> > without an OS?  Will your Ethernet interface be a full custom or are you 
> > going to use an Ethernet module that provides a serial link to your CPU?
> 
> I found a simple Ethernet controller on fpga4fun:
>     http://www.fpga4fun.com/10BASE-T.html
> 
> I plan on creating a simple buffer which receives internal pipe stage
> information at each CPU clock, and then transmits that data back out in
> real-time to some a port being monitored by my debugger.  This will allow
> me to then constantly monitor the machine state.  I can also then encode
> external source level single-step debugging, assembly tools, make even
> program changes in real-time, etc., to complete the entire toolset.
> 
> I developed my own kernel and primitive OS back in the late 90s, early
> 00s.  I will be using a modified version of that as the ISA I'm using
> is somewhat different than the actual 80386 ISA in (except in
> compatibility mode, which I will probably add last).
> 
> I'm thinking I would also like to figure out and test timing on a fixed
> SVGA video mode for a 1920x1080 signal at 60 Hz, and just hard-code that
> video mode and use it for everything the machine does until I can later
> add other modes.  And the same for a DRAM controller so I can have that
> consistent and normal access to memory, Ethernet, and VGA throughout all
> of my development.

I've since given this some additional thought and have decided I'll
transmit everything over Ethernet.  In this way I can create several
virtual screens and simply write to memory ranges and have them be
transmitted when possible.

Best regards,
Rick C. Hodgin

rickman wrote:


> 
> There is some interesting software they provide for working with Altera
> FPGAs called Quartus.  It will let you synthesize your designs and
> measure the size.  Then you can tell what size part it will fit.  No
> guesswork required.  :)
> 
Xilinx has similar capabilities.  You can desing for an arbitrary family,
then it will tell you the smalles device it will actually fit into.

I only use Xilinx, but some research SEEMS to indicate to me that
Xilinx devices may be a good deal cheaper than Altera.

All of the rest of Rick's comments are very good, and apply equally
to Xilinx.

Jon