Comparing Quality of Results of FPGA CAD Tools

I am a full professor in a US school and do research
in the area of synthesis. I also teach logic design for
Undergraduate students. I had a six month sabbatical recently
in a design house and I used many FPGA cad tools. I would
like to shed my experiences in this group.

I worked on 15 big designs, already coded, targeting both virtexII
and StratixII. All the designs were in verilog and I used
Xilinx XST and Altera QNS at the front end. I spent lot
of time to see the quality of results from the synthesis
tools. For 11 designs, QNS won both in area and final
fmax. XST was not even comparable in the quality of results.
QNS compiler seems to do very  good job compared to
XST. Also, QNS does very good job in removing redundant logic
and registers. So in my experience, QNS is a much better logic synthesis 
tools compared to XST. 

At the end of my sabbatical, I was able to use the latest (beta) synplify PRO.
I did not have much time, but I did run these 15 designs targeting
StartixII, as I was interested in comparing with the best known results.
Synplify Pro did excellent job in implementing operators,
and it found optimal  five, six and seven inputs functions
on the critical paths. 

For my ten designs, Pro results were superior in terms of area and fmax
compared to QNS. Synplify Pro has a very fast run time.
For the remaining five designs, QNS seems to remove
lot of redundant logic and registers, which pro did not remove. 
I did not have time to analyze these designs. QNS area was much
smaller for these five designs. 

I am back to my school and I use free XST and QNS tools.
I am going to do more research using these tools. I would like
to share my experience in this group. I am also interested
in listening the quality of results from various tools.

Prof. John Smith
a2003zz@yahoo.com

"John Smith" <a2003zz@yahoo.com> wrote in message
news:b97fd375.0408051432.6baf5760@posting.google.com...
> I am a full professor in a US school and do research
> in the area of synthesis. I also teach logic design for
> Undergraduate students. I had a six month sabbatical recently
> in a design house and I used many FPGA cad tools. I would
> like to shed my experiences in this group.
>
> I worked on 15 big designs, already coded, targeting both virtexII
> and StratixII. All the designs were in verilog and I used
> Xilinx XST and Altera QNS at the front end. I spent lot
> of time to see the quality of results from the synthesis
> tools. For 11 designs, QNS won both in area and final
> fmax. XST was not even comparable in the quality of results.
> QNS compiler seems to do very  good job compared to
> XST. Also, QNS does very good job in removing redundant logic
> and registers. So in my experience, QNS is a much better logic synthesis
> tools compared to XST.

I'm not sure what this is telling us. It looks like you compared the
fmax of some designs in VirtexII (quite old technology) and
StratixII (quite new/future technology), and observed that the StratixII
implementation was faster.

From this you deduced that the Altera synthesis was better.

What am I missing here?

On 5 Aug 2004 15:32:23 -0700, a2003zz@yahoo.com (John Smith) wrote:

>I am a full professor in a US school and do research
>in the area of synthesis. I also teach logic design for
>Undergraduate students. I had a six month sabbatical recently
>in a design house and I used many FPGA cad tools. I would
>like to shed my experiences in this group.
>

Let's see:
 - name is John Smith
 - full professor at US school, but no mention of school name
 - yahoo e-mail address
 - Having attended engineering school, I realize that English is 
not a top priority for students or faculty. Even so, the phrase "I
would like to shed my experiences" is not exactly
confidence-inspiring.

I suppose this could be legit, but the ol' bogosity meter is sitting
near full scale.  For starters, could you give us the university and
department names?

Thanks,
Bob Perlman
Cambrian Design Works
  

Pete Fraser wrote:
> "John Smith" <a2003zz@yahoo.com> wrote in message
> news:b97fd375.0408051432.6baf5760@posting.google.com...
> 
>>I am a full professor in a US school and do research
>>in the area of synthesis. I also teach logic design for

[snip]

> 
> From this you deduced that the Altera synthesis was better.
> 
> What am I missing here?

My B.S. detectors are hitting full scale deflection on this one!

"John Smith"?    Pseudo-anonymous name, anonymous email, simple 
grammatical errors, explicitly saying "full professor", not identifying 
which school... nah....

But why?

John Williams wrote:
> Pete Fraser wrote:
> 
>> "John Smith" <a2003zz@yahoo.com> wrote in message
>> news:b97fd375.0408051432.6baf5760@posting.google.com...
>>
>>> I am a full professor in a US school and do research
>>> in the area of synthesis. I also teach logic design for
> 
> 
> [snip]
> 
>>
>> From this you deduced that the Altera synthesis was better.
>>
>> What am I missing here?
> 
> 
> My B.S. detectors are hitting full scale deflection on this one!
> 
> "John Smith"?    Pseudo-anonymous name, anonymous email, simple 
> grammatical errors, explicitly saying "full professor", not identifying 
> which school... nah....
> 
> But why?

Perhaps the author is the Prof. John Smith that google turns up here :)
http://www.a2zcolleges.com/adm/samplereco.html
-jg

From his IP address he's one
CustName:   J VASUDEVAMURTHY

I found an email address on Google

jagadeesh.vasudevamurthy@Xilinx.COM

How very strange!

"Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message
news:eog5h0hguncjmoiu7b3cq6gu6beihebhl3@4ax.com...
> On 5 Aug 2004 15:32:23 -0700, a2003zz@yahoo.com (John Smith) wrote:
>
> >I am a full professor in a US school and do research
> >in the area of synthesis. I also teach logic design for
> >Undergraduate students. I had a six month sabbatical recently
> >in a design house and I used many FPGA cad tools. I would
> >like to shed my experiences in this group.
> >
>
> Let's see:
>  - name is John Smith
>  - full professor at US school, but no mention of school name
>  - yahoo e-mail address
>  - Having attended engineering school, I realize that English is
> not a top priority for students or faculty. Even so, the phrase "I
> would like to shed my experiences" is not exactly
> confidence-inspiring.
>
> I suppose this could be legit, but the ol' bogosity meter is sitting
> near full scale.  For starters, could you give us the university and
> department names?
>
> Thanks,
> Bob Perlman
> Cambrian Design Works
>
>

Pete Fraser wrote:
> 
> "John Smith" <a2003zz@yahoo.com> wrote in message
> news:b97fd375.0408051432.6baf5760@posting.google.com...
> > I am a full professor in a US school and do research
> > in the area of synthesis. I also teach logic design for
> > Undergraduate students. I had a six month sabbatical recently
> > in a design house and I used many FPGA cad tools. I would
> > like to shed my experiences in this group.
> >
> > I worked on 15 big designs, already coded, targeting both virtexII
> > and StratixII. All the designs were in verilog and I used
> > Xilinx XST and Altera QNS at the front end. I spent lot
> > of time to see the quality of results from the synthesis
> > tools. For 11 designs, QNS won both in area and final
> > fmax. XST was not even comparable in the quality of results.
> > QNS compiler seems to do very  good job compared to
> > XST. Also, QNS does very good job in removing redundant logic
> > and registers. So in my experience, QNS is a much better logic synthesis
> > tools compared to XST.
> 
> I'm not sure what this is telling us. It looks like you compared the
> fmax of some designs in VirtexII (quite old technology) and
> StratixII (quite new/future technology), and observed that the StratixII
> implementation was faster.
> 
> From this you deduced that the Altera synthesis was better.
> 
> What am I missing here?

How exactly is Virtex II considered "old" technology.  Virtex 2 is the
newest, fastest parts that Xilinx has.  Virtex2pro may be a bit
newer/faster, but they are not the same generic parts, they all include
Power PC CPUs internally driving up the cost considerably.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Rotund Phase wrote:
> From his IP address he's one
> CustName:   J VASUDEVAMURTHY

How'd you figure that then?

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:41133277.590BD487@yahoo.com...

>
> How exactly is Virtex II considered "old" technology.  Virtex 2 is the
> newest, fastest parts that Xilinx has.  Virtex2pro may be a bit
> newer/faster, but they are not the same generic parts, they all include
> Power PC CPUs internally driving up the cost considerably.
>
I guess "old" was the wrong term.
I was just pointing out that it might be more appropriate to compare
StratixII with Virtex4.

Pete,

You are correct.  4VLX25 ES samples are available, too.

Austin

Pete Fraser wrote:
> "rickman" <spamgoeshere4@yahoo.com> wrote in message
> news:41133277.590BD487@yahoo.com...
> 
> 
>>How exactly is Virtex II considered "old" technology.  Virtex 2 is the
>>newest, fastest parts that Xilinx has.  Virtex2pro may be a bit
>>newer/faster, but they are not the same generic parts, they all include
>>Power PC CPUs internally driving up the cost considerably.
>>
> 
> I guess "old" was the wrong term.
> I was just pointing out that it might be more appropriate to compare
> StratixII with Virtex4.
> 
>