Forums

SDRAM Controller on a cyclone dev kit

Started by Nick August 15, 2004
Hello,

I've been unsuccessfully trying to use the SDRAM on my MJL Cyclone dev
kit. I've tried the example (not very well documented) sold with the
dev kit, and tried the Altera IP Sdram controller.

The way i do it :
I connect the sdram controller to the sdram and use a small test
module to check it reads and writes. I start with the initialisation
sequence of the ram (nop for 100�s then load register), i write at the
adress 0...00 and then at adress 0..01, read alternatively each adress
with a pause and print the output on a digit. 
At best i have something funny on the digit, which is most of the time
not what i want, at worst i have the digit blank.

On the Altera IP, i use the built it pll on clk1 to drive the sdram
(since it seems from the specsheets that the output of pll1 is
connected to the sdram clk) and either the clk1 or another clk to feed
the whole. (i tried at 100 and 33 MHz).

With the MJL Cyclone dev kit i use the pll1 to fee the sdram and the
sdram controller.


I've tried to simulate (I use Quartus 4.1) and it seems that the
simulation is completly out of its head. I have states transitions
BEFORE the signal driving it actually arrives. Are the simulation
reliable with the plls ?

Do you please have some idea of what i am doing wrong ?

Thank you very much
Nick Charles 
Are you trying to access on board SDRAM?  Do you know whether you meet your
timing for SDRAM?  Most of time, that is the case unless your code is
wrong.  I also have NIOS I Cyclone Dev. board, but didn't get a chance to
play with it.  Which board do you have?

Kevin  

I am trying to access the board SDRAM. I should be meeting the timing
of the ram, at least according to the documentation of the sdram
controller and the documentation of the ram.

I have the MJL Cyclone dev kit (www.mjl.com), with 8 MB Micron SDRAM
 

On Wed, 18 Aug 2004 16:49:05 -0400, "kattice" <kattice@hotmail.com>
wrote:

>Are you trying to access on board SDRAM? Do you know whether you meet your >timing for SDRAM? Most of time, that is the case unless your code is >wrong. I also have NIOS I Cyclone Dev. board, but didn't get a chance to >play with it. Which board do you have? > >Kevin