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Is it possible to have a parameterized verilog module name in verilog or systemverilog?

Started by Unknown June 6, 2015
Hi,

I am trying create verilog module that can support parameterized instance name. I understand that the signal width and other such things can be parameterized. But can we also parameterize the module instance name?

In following code, I am curious if there is any way SomeDynamicInstanceName can be parameterized also? I can try to use system verilog if that can help here 

My purpose is to be able to reuse the verilog gmon module (generic verilog module) for various types of signals.  But for a reason, I need to change the SomeDynamicInstanceName.  I have control of a verilog file where I instantiate gmon verilog module so I can pass the parameters.

Prompt response is greatly appreciated.

`timescale 1 ns/100 ps


module gmon 
#(
parameter WIDTH = 32
)
(Clk, Rst, SignalName);


// PCIE MST_BIF
input Clk;
input Rst;
input [WIDTH-1:0] SignalName;

// input [31:0] SignalName_ret




reg [WIDTH-1:0] SignalName_d1;
//reg [31:0] SignalName_d2;




always @ (posedge Clk) begin
SignalName_d1 <= SignalName;
// SignalName_d2 <= SignalName_ret;
end


wire b = some combinatroial log;


test_module #(.FIFOBUF_WIDTH(WIDTH)) SomeDynamicInstanceName (
.reset(Rst), //CHECK THIS -- ACTIVE HIGH
.wclk(Clk),
.out_data_valid(b),
.out_data(SignalName[WIDTH-1:0]),
.out_eom(1'b0),
.out_flush_file(1'b0),
.out_flush_pipe(1'b0)
);

cpandya@yahoo.com wrote:
 
> I am trying create verilog module that can support parameterized > instance name. I understand that the signal width and other such > things can be parameterized. But can we also parameterize the > module instance name?
> In following code, I am curious if there is any way > SomeDynamicInstanceName can be parameterized also? I can try > to use system verilog if that can help here
(snip) I didn't figure out from the example, so maybe you can explain again. I mostly don't use parameters, but often enough generate a new instance with a new name. I might have an eight bit register named reg8, and a 16 bit one named reg16, where others might name it reg with a parameter that is 8 or 16. But it is one or the other, not both. Well, I suppose one way to implement reg8 and reg16 is though instantiating reg with parameter 8 or 16, but another way is to use a program in some other language to generate source modules as appropriate. It is very easy, for example, with awk to generate appropriate modules with appropriate names. -- glen
I'd say your options are pretty limited.  

1.  Use a precompiler directive, which you can set when calling the synthesizer or simulator:
test_module #(.FIFOBUF_WIDTH(WIDTH)) 
`DynamicInstanceName 
( ...

2.  Use a generate-case to select between a few instance name options based on a parameter.

3.  Like the other respondent said, use Awk or TCL or some other scripting language to modify or write out HDL before running synth/sim.  You could probably just put the name into an include file and then include that:
test_module #(.FIFOBUF_WIDTH(WIDTH)) 
`inclue "Instancename.txt"
( ...

These are all a bit kludgey.
-Kevin
/sim.  You could probably just put the name into an include file and then include that:
> test_module #(.FIFOBUF_WIDTH(WIDTH)) > `inclue "Instancename.txt" > ( ...
I meant "include". You can even use Verilog to generate Verilog. Pretty kludgey, but I've done that. You have to run the Verilog-generating Verilog first. Better to use some other language.
I don't know how much control you need, but I was thinking, for option #2, you could control at least the numeric index of the name, I think.  For example:

parameter K = 4;
generate for (genvar j=K; j<=K; j=j+1) begin: gen_inst
test_module #() SomeInstName ();
end
endgenerate

In this case, I think your instance name would be something like gen_inst[4].SomeInstName, so you could at least change the index by changing K.
On Saturday, June 6, 2015 at 4:53:40 AM UTC-6, cpa...@yahoo.com wrote:
> Hi, > > I am trying create verilog module that can support parameterized instance name. I understand that the signal width and other such things can be parameterized. But can we also parameterize the module instance name? > > In following code, I am curious if there is any way SomeDynamicInstanceName can be parameterized also? I can try to use system verilog if that can help here > > My purpose is to be able to reuse the verilog gmon module (generic verilog module) for various types of signals. But for a reason, I need to change the SomeDynamicInstanceName. I have control of a verilog file where I instantiate gmon verilog module so I can pass the parameters. > > Prompt response is greatly appreciated. > > `timescale 1 ns/100 ps > > > module gmon > #( > parameter WIDTH = 32 > ) > (Clk, Rst, SignalName); > > > // PCIE MST_BIF > input Clk; > input Rst; > input [WIDTH-1:0] SignalName; > > // input [31:0] SignalName_ret > > > > > reg [WIDTH-1:0] SignalName_d1; > //reg [31:0] SignalName_d2; > > > > > always @ (posedge Clk) begin > SignalName_d1 <= SignalName; > // SignalName_d2 <= SignalName_ret; > end > > > wire b = some combinatroial log; > > > test_module #(.FIFOBUF_WIDTH(WIDTH)) SomeDynamicInstanceName ( > .reset(Rst), //CHECK THIS -- ACTIVE HIGH > .wclk(Clk), > .out_data_valid(b), > .out_data(SignalName[WIDTH-1:0]), > .out_eom(1'b0), > .out_flush_file(1'b0), > .out_flush_pipe(1'b0) > );
Take a look at Verilog-mode (AUTO) for Emacs, if you use Emacs. You wont get dynamic instance names with AUTO, but it is easy to do special things per instance via AUTO_TEMPLATEs. Like if instance name is 'gmon0' connect bit n to input y. If instance name is 'gmon1' then connect bit n+1 to input y etc. This could offer a new path to solve your issue.
On Sat, 6 Jun 2015 03:53:37 -0700 (PDT)
cpandya@yahoo.com wrote:

> Hi, > > I am trying create verilog module that can support > parameterized instance name. I understand that the signal > width and other such things can be parameterized. But can we > also parameterize the module instance name?
There is a trivial example here: http://rosettacode.org/wiki/Four_bit_adder search page for Professional Code - with test bench Notice that there is no width parameter nor global to indicate how wide Multibit_Adder should be. Jan Coombs -- email valid, else fix dots and hyphen jan4clf2014@murrayhyphenmicroftdotcodotuk