DC Blocker

Hi all,

I need to implement DC blocker in FPGA. Data samples are coming at every
clock cycle.

My original idea was to implement high pass filter as in formula below:

y[n] = x[n] - x[n-1] + p*y[n-1]

However it seems to me that I cannot achieve this with the given data
rate. I am unable to calculate output by the time when I need it in
feedback loop for the next sample.

Is there some way to do this that I don't see?
If not, I was thinking of finding mean value of signal and subtracting it
from signal in order to clear DC.
However, I do not know how to determine appropriate number of samples for
this and do i do this by FIR filtering with all coefficients equal to
1/N?

Thank you in advance.

---------------------------------------
Posted through http://www.FPGARelated.com

>Hi all,
>
>I need to implement DC blocker in FPGA. Data samples are coming at every
>clock cycle.
>
>My original idea was to implement high pass filter as in formula below:
>
>y[n] = x[n] - x[n-1] + p*y[n-1]
>
>However it seems to me that I cannot achieve this with the given data
>rate. I am unable to calculate output by the time when I need it in
>feedback loop for the next sample.
>

you can, just put one delay stage(register) on input to get x[n-1] and one
on output to get y[n-1], multiply by p and the circuit will do the job at
data rate. The mult output should not be registered and this may be speed
bottleneck. Moreover the above subtraction/addition cannot be pipelined
i.e. result should arrive at same clock edge. What is your data rate
(system clock) and device?

>Is there some way to do this that I don't see?
>If not, I was thinking of finding mean value of signal and subtracting
it
>from signal in order to clear DC.
>However, I do not know how to determine appropriate number of samples
for
>this and do i do this by FIR filtering with all coefficients equal to
>1/N?
>
This an alternative but you may need long delay stages to filter off dc
only.
for n stages, design n stages of delay, subtract current input from last
stage and accumulate/scale.

Kaz
---------------------------------------
Posted through http://www.FPGARelated.com

Hm.. I tought that multiplication cannot be implemented without delay.

This could cause timing issues to my knowledge.

Moreover, full formula is 

y[n] = Q {x[n] - x[n-1] + p*y[n-1] - e[n-1]}
e[n] = x[n] - x[n-1] + p*y[n-1] - e[n-1] - y[n]

Error is difference between output before and after quantization.
I asked for the initial one because even that i don't know how to
implement.

if x1 appears at t1, corresponding y1 is ready at earlies at t2=t1+1. If I
register subtracting operation as well, e1 is available at t3=t1+1.
However x2 arrives at t2 and neither y1 (corresponding y[n-1]) or e1 are
ready at that time.



---------------------------------------
Posted through http://www.FPGARelated.com

>Hm.. I tought that multiplication cannot be implemented without delay.
>
>This could cause timing issues to my knowledge.
>
>Moreover, full formula is 
>
>y[n] = Q {x[n] - x[n-1] + p*y[n-1] - e[n-1]}
>e[n] = x[n] - x[n-1] + p*y[n-1] - e[n-1] - y[n]
>
>Error is difference between output before and after quantization.
>I asked for the initial one because even that i don't know how to
>implement.
>
>if x1 appears at t1, corresponding y1 is ready at earlies at t2=t1+1. If
I
>register subtracting operation as well, e1 is available at t3=t1+1.
>However x2 arrives at t2 and neither y1 (corresponding y[n-1]) or e1 are
>ready at that time.
>
>
>
>---------------------------------------
>Posted through http://www.FPGARelated.com

As such you got very long combinatorial paths running from mult input
right through adders/subtractors. Unless your speed is low enough you
can't do that in practice.

The fir subtraction is certainly doable but you need a long delay line
e.g. n = 1024 or more but depends on signal

Kaz
---------------------------------------
Posted through http://www.FPGARelated.com

On 10/22/2015 3:13 PM, b2508 wrote:
> Hm.. I tought that multiplication cannot be implemented without delay.
>
> This could cause timing issues to my knowledge.
>
> Moreover, full formula is
>
> y[n] = Q {x[n] - x[n-1] + p*y[n-1] - e[n-1]}
> e[n] = x[n] - x[n-1] + p*y[n-1] - e[n-1] - y[n]
>
> Error is difference between output before and after quantization.
> I asked for the initial one because even that i don't know how to
> implement.
>
> if x1 appears at t1, corresponding y1 is ready at earlies at t2=t1+1. If I
> register subtracting operation as well, e1 is available at t3=t1+1.
> However x2 arrives at t2 and neither y1 (corresponding y[n-1]) or e1 are
> ready at that time.

What is Q?

Y1 is ready at t1+delta which is a logic delay, not a clock cycle.  So 
don't sweat that.  If you need to pipeline this to meet timing 
constraints, you are in trouble, lol.

What clock rate are you shooting for?

-- 

Rick

In article <2Z-dnUTCaKvCqLTLnZ2dnUU7-VOdnZ2d@giganews.com>,
b2508 <108118@FPGARelated> wrote:
>Hm.. I tought that multiplication cannot be implemented without delay.
>
>This could cause timing issues to my knowledge.
>
>Moreover, full formula is 
>
>y[n] = Q {x[n] - x[n-1] + p*y[n-1] - e[n-1]}
>e[n] = x[n] - x[n-1] + p*y[n-1] - e[n-1] - y[n]
>
>Error is difference between output before and after quantization.
>I asked for the initial one because even that i don't know how to
>implement.
>
>if x1 appears at t1, corresponding y1 is ready at earlies at t2=t1+1. If I
>register subtracting operation as well, e1 is available at t3=t1+1.
>However x2 arrives at t2 and neither y1 (corresponding y[n-1]) or e1 are
>ready at that time.

Without really looking at your required function in detail (just noting
that it has feedback terms) - I'll just note in general.

The statement "multiplication cannot be implemented without delay" is 
false, in many ways.  It all depends on your processing requirements. 
What is your sample rate?  What are your bit widths?

You're processing clock does NOT need to be the same as your sample clock.
If you wish them to be the same - it may be easier for new FPGA users to 
design - then you MAY be able to run the multiplier full combinational - 
If you're sample rate is low enough.

The alternative (at a high level) is to buffer an input and output, and 
process with a faster processing clock.  Modern FPGA's these days can run 
DSP functions upwards to around 400-500 MHz.  This is likely much faster 
than your sample rate.

Regards,
Mark

>In article <2Z-dnUTCaKvCqLTLnZ2dnUU7-VOdnZ2d@giganews.com>,
>b2508 <108118@FPGARelated> wrote:
>>Hm.. I tought that multiplication cannot be implemented without delay.
>>
>>This could cause timing issues to my knowledge.
>>
>>Moreover, full formula is 
>>
>>y[n] = Q {x[n] - x[n-1] + p*y[n-1] - e[n-1]}
>>e[n] = x[n] - x[n-1] + p*y[n-1] - e[n-1] - y[n]
>>
>>Error is difference between output before and after quantization.
>>I asked for the initial one because even that i don't know how to
>>implement.
>>
>>if x1 appears at t1, corresponding y1 is ready at earlies at t2=t1+1. If
I
>>register subtracting operation as well, e1 is available at t3=t1+1.
>>However x2 arrives at t2 and neither y1 (corresponding y[n-1]) or e1
are
>>ready at that time.
>
>Without really looking at your required function in detail (just noting
>that it has feedback terms) - I'll just note in general.
>
>The statement "multiplication cannot be implemented without delay" is 
>false, in many ways.  It all depends on your processing requirements. 
>What is your sample rate?  What are your bit widths?
>
>You're processing clock does NOT need to be the same as your sample
clock.
>If you wish them to be the same - it may be easier for new FPGA users to

>design - then you MAY be able to run the multiplier full combinational -

>If you're sample rate is low enough.
>
>The alternative (at a high level) is to buffer an input and output, and 
>process with a faster processing clock.  Modern FPGA's these days can run

>DSP functions upwards to around 400-500 MHz.  This is likely much faster

>than your sample rate.
>
>Regards,
>Mark

OK, I was taught that it is always safer to put registers wherever you
can. I have no choice in my project but to have same sampling and
processing rate.

My rate is 100 MHz.
Input data or x[n] has data format - unsigned, 16 bit, 1 bit for integer.

Also, I am not sure how to select data widths after each of these
operations.

If x[n] and x[n-1] are 16/1 and their subtraction is 17 bit unsigned with
2 bit integers, how do I proceed with data width selection? Feedback loop
part is unclear to me. 
Also, should I use DSP48 for the multiplication with P or should I make it
somehow power of two and do it by shifting?

Q is quantization, or reducing number of samples after all these
operations.


---------------------------------------
Posted through http://www.FPGARelated.com

Mark Curry <gtwrek@sonic.net> wrote:

(snip)

> Without really looking at your required function in detail (just noting
> that it has feedback terms) - I'll just note in general.
 
> The statement "multiplication cannot be implemented without delay" is 
> false, in many ways.  It all depends on your processing requirements. 
> What is your sample rate?  What are your bit widths?

I would say that it is right, but not very useful.

Addition can't be implemented without delay, and for that matter
no filter can be.  Even wires have delay.

If you are lucky, you can do all processing within one sample
period, so one sample delay.  You have to include any delay from
the previous register, so you have less than one sample period.

But more often, you can live with a few cycles delay, and pipeline
the whole system. 
 
> You're processing clock does NOT need to be the same as your sample clock.
> If you wish them to be the same - it may be easier for new FPGA users to 
> design - then you MAY be able to run the multiplier full combinational - 
> If you're sample rate is low enough.
 
> The alternative (at a high level) is to buffer an input and output, and 
> process with a faster processing clock.  Modern FPGA's these days can run 
> DSP functions upwards to around 400-500 MHz.  This is likely much faster 
> than your sample rate.

-- glen

On Thu, 22 Oct 2015 13:18:14 -0500, b2508 wrote:

> Hi all,
> 
> I need to implement DC blocker in FPGA. Data samples are coming at every
> clock cycle.
> 
> My original idea was to implement high pass filter as in formula below:
> 
> y[n] = x[n] - x[n-1] + p*y[n-1]
> 
> However it seems to me that I cannot achieve this with the given data
> rate. I am unable to calculate output by the time when I need it in
> feedback loop for the next sample.
> 
> Is there some way to do this that I don't see?
> If not, I was thinking of finding mean value of signal and subtracting
> it from signal in order to clear DC.
> However, I do not know how to determine appropriate number of samples
> for this and do i do this by FIR filtering with all coefficients equal
> to 1/N?

There are other ways to implement high-pass filters.  I'm not much of an 
FPGA guy, but this one may help.  I'm going to rearrange your 
nomenclature:

u: input
y: output
x: state variable

y[n] = u[n] - x[n-1]
x[n] = d * y[n]

For d << 1 this should be pretty robust even if you have to toss in extra 
delays (i.e., x[n] = d * y[n - m], for some integer value of m).

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

On 10/22/2015 4:50 PM, b2508 wrote:
>> In article <2Z-dnUTCaKvCqLTLnZ2dnUU7-VOdnZ2d@giganews.com>,
>> b2508 <108118@FPGARelated> wrote:
>>> Hm.. I tought that multiplication cannot be implemented without delay.
>>>
>>> This could cause timing issues to my knowledge.
>>>
>>> Moreover, full formula is
>>>
>>> y[n] = Q {x[n] - x[n-1] + p*y[n-1] - e[n-1]}
>>> e[n] = x[n] - x[n-1] + p*y[n-1] - e[n-1] - y[n]
>>>
>>> Error is difference between output before and after quantization.
>>> I asked for the initial one because even that i don't know how to
>>> implement.
>>>
>>> if x1 appears at t1, corresponding y1 is ready at earlies at t2=t1+1. If
> I
>>> register subtracting operation as well, e1 is available at t3=t1+1.
>>> However x2 arrives at t2 and neither y1 (corresponding y[n-1]) or e1
> are
>>> ready at that time.
>>
>> Without really looking at your required function in detail (just noting
>> that it has feedback terms) - I'll just note in general.
>>
>> The statement "multiplication cannot be implemented without delay" is
>> false, in many ways.  It all depends on your processing requirements.
>> What is your sample rate?  What are your bit widths?
>>
>> You're processing clock does NOT need to be the same as your sample
> clock.
>> If you wish them to be the same - it may be easier for new FPGA users to
>
>> design - then you MAY be able to run the multiplier full combinational -
>
>> If you're sample rate is low enough.
>>
>> The alternative (at a high level) is to buffer an input and output, and
>> process with a faster processing clock.  Modern FPGA's these days can run
>
>> DSP functions upwards to around 400-500 MHz.  This is likely much faster
>
>> than your sample rate.
>>
>> Regards,
>> Mark
>
> OK, I was taught that it is always safer to put registers wherever you
> can. I have no choice in my project but to have same sampling and
> processing rate.
>
> My rate is 100 MHz.
> Input data or x[n] has data format - unsigned, 16 bit, 1 bit for integer.
>
> Also, I am not sure how to select data widths after each of these
> operations.
>
> If x[n] and x[n-1] are 16/1 and their subtraction is 17 bit unsigned with
> 2 bit integers, how do I proceed with data width selection? Feedback loop
> part is unclear to me.
> Also, should I use DSP48 for the multiplication with P or should I make it
> somehow power of two and do it by shifting?
>
> Q is quantization, or reducing number of samples after all these
> operations.

Do you know the value of P?  Multiplies are done by shifting and adding. 
  I don't know which chip you are planning to use, but all the 
multipliers I know of require pipelining, the only option is how many 
stages, 1, 2, etc...  Since P is a constant (it *is* a constant, right?) 
you only need to use adders for the 1s, or if there are long runs of 1s 
or 0s, you can subtract at the lsb of the run and add in at the bit just 
past the msb of the run.  The point is you may not need to use a built 
in multiplier.

Your filter seems very complex for a feedback filter.  Is there some 
special need driving this?  Can you use a simpler filter?

-- 

Rick