Using an FPGA to drive the 80386 CPU on a real motherboard

I have a desire to create an 80386 CPU in FPGA form, one which will plug in
to the 132-pin socket of existing 80386 motherboard as a replacement CPU.  I
want to be able to provide the features of the 80386 on that machine, but
through my FPGA, to then allow me to extend the ISA to include other
instructions and abilities.

Does anybody have an experience or advice in creating an FPGA-based CPU that
connects to a real hardware device and simulates the real device's abilities?

For example, the 80386 uses 5V and the Altera board I have drives 1.xV and
3.3V max, so I'd have to use a level converter.  At speeds up to a max of
40 MHz, would there be any issues?

Also, I'd like to create a "monitor board," which is a board with a 132-
pin male socket connecting to the CPU on one side, and a 132-pin female
socket on the other side to which a real 80386 CPU would connect, and then
to be able to pull signals off the wires between the CPU socket and the
CPU itself.  I had assumed I would use opto-isolation for this, but I don't
know if it would work or be best.

In addition, and specific to the 80386 CPU, AMD manufactured an Am386 CPU
that is 100% compatible with the Intel 80386, but it has the ability to
underclock down to even 0 MHz in a standby mode (allowing it to consume
only 0.001 Watts).  I'm wondering if anyone has any experience underclocking
an 80386 motherboard down into the KHz range, or even Hz range, and if it
would still work at those slow speeds on the board?

My goals in slowing down the CPU are to detect and isolate timing protocols,
which I can then scale up to higher speeds once identified.

In any event, any help or advice is appreciated.  Thank you.

Best regards,
Rick C. Hodgin

On 4/5/2016 3:15 PM, Rick C. Hodgin wrote:
> I have a desire to create an 80386 CPU in FPGA form, one which will plug in
> to the 132-pin socket of existing 80386 motherboard as a replacement CPU.  I
> want to be able to provide the features of the 80386 on that machine, but
> through my FPGA, to then allow me to extend the ISA to include other
> instructions and abilities.
>
> Does anybody have an experience or advice in creating an FPGA-based CPU that
> connects to a real hardware device and simulates the real device's abilities?
>
> For example, the 80386 uses 5V and the Altera board I have drives 1.xV and
> 3.3V max, so I'd have to use a level converter.  At speeds up to a max of
> 40 MHz, would there be any issues?

Even at 40 MHz you will need to be tidy with your routing to keep the 
signals from ringing, etc.  I don't know the details of the 386 chip I/O 
specs, but quickswitch type parts will do a good job of level shifting 
between 3.33 and 5 volts without adding much delay.  Because the signal 
passes between the source and drain there is very little delay.  They 
don't pull up to 5 volts, but 5 volt logic usually only need 2.x volts 
anyway.  But you'll need to check the parts you are interfacing to on 
the mother board or just give it a wing.  You can add pullups on the 5 
volt side, but pullups tend to be slow.  Even a few ns of added delay 
can cause a 386 not to work.  Many of the early mobos had timing issues 
because of the TTL logic used.  I don't think 386 mobos had chip sets in 
place of the TTL, did they?


> Also, I'd like to create a "monitor board," which is a board with a 132-
> pin male socket connecting to the CPU on one side, and a 132-pin female
> socket on the other side to which a real 80386 CPU would connect, and then
> to be able to pull signals off the wires between the CPU socket and the
> CPU itself.  I had assumed I would use opto-isolation for this, but I don't
> know if it would work or be best.

Opto-isolation is pretty slow compared to 40 MHz, but maybe there are 
faster converters these days.  Why do you need isolation?


> In addition, and specific to the 80386 CPU, AMD manufactured an Am386 CPU
> that is 100% compatible with the Intel 80386, but it has the ability to
> underclock down to even 0 MHz in a standby mode (allowing it to consume
> only 0.001 Watts).  I'm wondering if anyone has any experience underclocking
> an 80386 motherboard down into the KHz range, or even Hz range, and if it
> would still work at those slow speeds on the board?

No experience, but the parts that would give trouble at slow clocks were 
the NMOS devices that went out long before the 386.  Certainly TTL and 
CMOS don't normally have a problem with slow clocking.


> My goals in slowing down the CPU are to detect and isolate timing protocols,
> which I can then scale up to higher speeds once identified.
>
> In any event, any help or advice is appreciated.  Thank you.

I have a book somewhere on the ISA bus with timing info.  ISA was never 
fully specified.  I think there was an effort to produce a spec, but it 
got canned and retracted at some point.  You can't even find draft 
versions of it now.  But that was more of an 8086/80286 thing.  I'm not 
sure the ISA bus was still mapped directly to the 386 bus.  I just don't 
remember.

-- 

Rick

On Tuesday, April 5, 2016 at 4:13:28 PM UTC-4, rickman wrote:
> On 4/5/2016 3:15 PM, Rick C. Hodgin wrote:
> > In addition, and specific to the 80386 CPU, AMD manufactured an Am386 CPU
> > that is 100% compatible with the Intel 80386, but it has the ability to
> > underclock down to even 0 MHz in a standby mode (allowing it to consume
> > only 0.001 Watts).  I'm wondering if anyone has any experience underclocking
> > an 80386 motherboard down into the KHz range, or even Hz range, and if it
> > would still work at those slow speeds on the board?
> 
> No experience, but the parts that would give trouble at slow clocks were 
> the NMOS devices that went out long before the 386.  Certainly TTL and 
> CMOS don't normally have a problem with slow clocking.

I assume the entire system is clocked off the single source?  So, would it
be as simple as removing the crystal circuit and replacing it with a soft
circuit operating at the same frequency driven from an FPGA output?  And
then taking the FPGA output and bringing it down slowly to underclock the
system?

I have two standard 80386 motherboards, and one 80386 motherboard with an
expansion socket.  I also have an 80486 motherboard with an i80486DX, and
two Pentium motherboards, 33 MHz and 60 MHz I believe.

Here's an online image I found which matches the 80386 I'm interested in
underlcocking:

    http://www.armanax.com/placa-base-m321-rev-2-5.html

It has an 80 MHz timing circuit, as the clock speed for the 80386s were
always double-pumped.

I want to get a case, power supply, VGA and MDA setup on it.  I have a
custom 80386 OS I wrote that I'll use for bootup and testing (loads
from a floppy disk).  I would write a simple test algorithm that does
some screen output, processes keystrokes, mouse movement, etc., and
have that test running as it's underclocked... assuming I'm on the
right path.

Best regards,
Rick C. Hodgin

On Tuesday, April 5, 2016 at 4:13:28 PM UTC-4, rickman wrote:
> On 4/5/2016 3:15 PM, Rick C. Hodgin wrote:
> > I have a desire to create an 80386 CPU in FPGA form, one which will plug in
> > to the 132-pin socket of existing 80386 motherboard as a replacement CPU.  I
> > want to be able to provide the features of the 80386 on that machine, but
> > through my FPGA, to then allow me to extend the ISA to include other
> > instructions and abilities.
> >
> > Does anybody have an experience or advice in creating an FPGA-based CPU that
> > connects to a real hardware device and simulates the real device's abilities?
> >
> > For example, the 80386 uses 5V and the Altera board I have drives 1.xV and
> > 3.3V max, so I'd have to use a level converter.  At speeds up to a max of
> > 40 MHz, would there be any issues?
> 
> Even at 40 MHz you will need to be tidy with your routing to keep the 
> signals from ringing, etc.

If I can get the machine underclocked, I'd like to bring it down into the
low KHz or even Hz range if possible, but something 100 KHz or lower at
least.

I envision the Cyclone V GX being mounted a couple inches above the 80386
socket.  I would use the HSMC to GPIO port to connect to the CPU socket.

I had considered at first using the co-processor socket and emulating the
80387 ISA at first.  I may still do that, but regardless, there are only
90 pins that are active on the 80386, and 64 of those are direct address
and data pins, with another 20 being control pins for when those lines
are active, and in what mode they're active.

There really isn't much logic involved in hooking up an 80386, which is
why I'm attempting this project.

To be honest, I wouldn't even mind dipping back down to a 4.77 MHz 8086
system and starting there as part of the ISA I'll support for the 80386
contains a full 8086 subset.

> I don't know the details of the 386 chip I/O 
> specs, but quickswitch type parts will do a good job of level shifting 
> between 3.33 and 5 volts without adding much delay.  Because the signal 
> passes between the source and drain there is very little delay.  They 
> don't pull up to 5 volts, but 5 volt logic usually only need 2.x volts 
> anyway.  But you'll need to check the parts you are interfacing to on 
> the mother board or just give it a wing.  You can add pullups on the 5 
> volt side, but pullups tend to be slow.  Even a few ns of added delay 
> can cause a 386 not to work.  Many of the early mobos had timing issues 
> because of the TTL logic used.

Excellent information, thank you.

> I don't think 386 mobos had chip sets in place of the TTL, did they?

Not originally, but later on.  These motherboards were manufactured in
the early 90s, and came with Am386 CPUs manufactured in 91 or 92.  I
believe the boards I have had switched to chip sets by then.

> > Also, I'd like to create a "monitor board," which is a board with a 132-
> > pin male socket connecting to the CPU on one side, and a 132-pin female
> > socket on the other side to which a real 80386 CPU would connect, and then
> > to be able to pull signals off the wires between the CPU socket and the
> > CPU itself.  I had assumed I would use opto-isolation for this, but I don't
> > know if it would work or be best.
> 
> Opto-isolation is pretty slow compared to 40 MHz, but maybe there are 
> faster converters these days.  Why do you need isolation?

I may not need it.  However, when I was working on stepper motors back
in the mid-90s, I believe we used them to maintain a low power draw on
the circuits we were monitoring.

> > In addition, and specific to the 80386 CPU, AMD manufactured an Am386 CPU
> > that is 100% compatible with the Intel 80386, but it has the ability to
> > underclock down to even 0 MHz in a standby mode (allowing it to consume
> > only 0.001 Watts).  I'm wondering if anyone has any experience underclocking
> > an 80386 motherboard down into the KHz range, or even Hz range, and if it
> > would still work at those slow speeds on the board?
> 
> No experience, but the parts that would give trouble at slow clocks were 
> the NMOS devices that went out long before the 386.  Certainly TTL and 
> CMOS don't normally have a problem with slow clocking.

From what I've read, Intel's 80386 CPUs would not clock below 10 MHz well.
But AMD's would clock down to any clock speed including 0 MHz.  It's why
I've wanted to try to target these systems which came with the Am386 CPU,
for their underclocking abilities.

> > My goals in slowing down the CPU are to detect and isolate timing protocols,
> > which I can then scale up to higher speeds once identified.
> >
> > In any event, any help or advice is appreciated.  Thank you.
> 
> I have a book somewhere on the ISA bus with timing info.  ISA was never 
> fully specified.  I think there was an effort to produce a spec, but it 
> got canned and retracted at some point.  You can't even find draft 
> versions of it now.  But that was more of an 8086/80286 thing.  I'm not 
> sure the ISA bus was still mapped directly to the 386 bus.  I just don't 
> remember.

IIRC, it operated at 4.77 MHz for 8-bit bus, and 6 MHz or 8 MHz for the
16-bit bus.  I don't know if that speed is required, or if it's the
standard clock speed when the system was operating at its normal clock
speed as would be setup by early BIOS during boot. I assume once it boots
up, the entire system can be overclocked or underclocked by altering the
frequency emitted by the clock circuit, and the whole system would rise
and fall in relative speed parity.  Just a guess though.

Best regards,
Rick C. Hodgin

On 4/5/2016 5:11 PM, Rick C. Hodgin wrote:
> On Tuesday, April 5, 2016 at 4:13:28 PM UTC-4, rickman wrote:
>> On 4/5/2016 3:15 PM, Rick C. Hodgin wrote:
>>> I have a desire to create an 80386 CPU in FPGA form, one which will plug in
>>> to the 132-pin socket of existing 80386 motherboard as a replacement CPU.  I
>>> want to be able to provide the features of the 80386 on that machine, but
>>> through my FPGA, to then allow me to extend the ISA to include other
>>> instructions and abilities.
>>>
>>> Does anybody have an experience or advice in creating an FPGA-based CPU that
>>> connects to a real hardware device and simulates the real device's abilities?
>>>
>>> For example, the 80386 uses 5V and the Altera board I have drives 1.xV and
>>> 3.3V max, so I'd have to use a level converter.  At speeds up to a max of
>>> 40 MHz, would there be any issues?
>>
>> Even at 40 MHz you will need to be tidy with your routing to keep the
>> signals from ringing, etc.
>
> If I can get the machine underclocked, I'd like to bring it down into the
> low KHz or even Hz range if possible, but something 100 KHz or lower at
> least.

Running with a slow clock doesn't assure a lack of problems from edge 
rates.  The edges usually are still just as fast and that is what 
creates problems.


> I envision the Cyclone V GX being mounted a couple inches above the 80386
> socket.  I would use the HSMC to GPIO port to connect to the CPU socket.

I don't know about the HSMC port, but I don't think you need anything 
special for a 40 MHz interface.


> I had considered at first using the co-processor socket and emulating the
> 80387 ISA at first.  I may still do that, but regardless, there are only
> 90 pins that are active on the 80386, and 64 of those are direct address
> and data pins, with another 20 being control pins for when those lines
> are active, and in what mode they're active.
>
> There really isn't much logic involved in hooking up an 80386, which is
> why I'm attempting this project.
>
> To be honest, I wouldn't even mind dipping back down to a 4.77 MHz 8086
> system and starting there as part of the ISA I'll support for the 80386
> contains a full 8086 subset.
>
>> I don't know the details of the 386 chip I/O
>> specs, but quickswitch type parts will do a good job of level shifting
>> between 3.33 and 5 volts without adding much delay.  Because the signal
>> passes between the source and drain there is very little delay.  They
>> don't pull up to 5 volts, but 5 volt logic usually only need 2.x volts
>> anyway.  But you'll need to check the parts you are interfacing to on
>> the mother board or just give it a wing.  You can add pullups on the 5
>> volt side, but pullups tend to be slow.  Even a few ns of added delay
>> can cause a 386 not to work.  Many of the early mobos had timing issues
>> because of the TTL logic used.
>
> Excellent information, thank you.
>
>> I don't think 386 mobos had chip sets in place of the TTL, did they?
>
> Not originally, but later on.  These motherboards were manufactured in
> the early 90s, and came with Am386 CPUs manufactured in 91 or 92.  I
> believe the boards I have had switched to chip sets by then.

I recall that because there was no "standard" for the design of the 
motherboard other than what IBM had done, there were some differences 
between the various chip sets.  In those days they *were* chip sets as 
the whole shebang didn't end up in one chip like was used later and 
still called a "chip set".  lol


>>> Also, I'd like to create a "monitor board," which is a board with a 132-
>>> pin male socket connecting to the CPU on one side, and a 132-pin female
>>> socket on the other side to which a real 80386 CPU would connect, and then
>>> to be able to pull signals off the wires between the CPU socket and the
>>> CPU itself.  I had assumed I would use opto-isolation for this, but I don't
>>> know if it would work or be best.
>>
>> Opto-isolation is pretty slow compared to 40 MHz, but maybe there are
>> faster converters these days.  Why do you need isolation?
>
> I may not need it.  However, when I was working on stepper motors back
> in the mid-90s, I believe we used them to maintain a low power draw on
> the circuits we were monitoring.

Optos are the opposite of low power draw on busses.  Enough current is 
required to drive an LED on the sensing side.  Optos are typically used 
to provide isolation from circuits that can have ground swings or 
otherwise be noisy or have high voltage spikes, like motor circuits.


>>> In addition, and specific to the 80386 CPU, AMD manufactured an Am386 CPU
>>> that is 100% compatible with the Intel 80386, but it has the ability to
>>> underclock down to even 0 MHz in a standby mode (allowing it to consume
>>> only 0.001 Watts).  I'm wondering if anyone has any experience underclocking
>>> an 80386 motherboard down into the KHz range, or even Hz range, and if it
>>> would still work at those slow speeds on the board?
>>
>> No experience, but the parts that would give trouble at slow clocks were
>> the NMOS devices that went out long before the 386.  Certainly TTL and
>> CMOS don't normally have a problem with slow clocking.
>
>  From what I've read, Intel's 80386 CPUs would not clock below 10 MHz well.
> But AMD's would clock down to any clock speed including 0 MHz.  It's why
> I've wanted to try to target these systems which came with the Am386 CPU,
> for their underclocking abilities.

I've forgotten more than I knew, lol.  That may be accurate.  I know the 
original NMOS circuits used dynamic circuits where values were 
remembered on capacitance and so had minimum clock rates.  Maybe even on 
CMOS designs they did the same thing.


>>> My goals in slowing down the CPU are to detect and isolate timing protocols,
>>> which I can then scale up to higher speeds once identified.
>>>
>>> In any event, any help or advice is appreciated.  Thank you.
>>
>> I have a book somewhere on the ISA bus with timing info.  ISA was never
>> fully specified.  I think there was an effort to produce a spec, but it
>> got canned and retracted at some point.  You can't even find draft
>> versions of it now.  But that was more of an 8086/80286 thing.  I'm not
>> sure the ISA bus was still mapped directly to the 386 bus.  I just don't
>> remember.
>
> IIRC, it operated at 4.77 MHz for 8-bit bus, and 6 MHz or 8 MHz for the
> 16-bit bus.  I don't know if that speed is required, or if it's the
> standard clock speed when the system was operating at its normal clock
> speed as would be setup by early BIOS during boot. I assume once it boots
> up, the entire system can be overclocked or underclocked by altering the
> frequency emitted by the clock circuit, and the whole system would rise
> and fall in relative speed parity.  Just a guess though.

It's not actually a synchronous bus.  Everything is timed by the read 
and write strobes with some other signals helping to control data 
directions on buffers.  It started with the 8088 I/O bus controls and 
remained compatible I believe, but I'm not sure.  If you don't mind 
stretching the cycles a bit it can be run synchronously.  I'll see if I 
can find that book.

-- 

Rick

On Tuesday, April 5, 2016 at 9:22:32 PM UTC-4, rickman wrote:
> On 4/5/2016 5:11 PM, Rick C. Hodgin wrote:
> > On Tuesday, April 5, 2016 at 4:13:28 PM UTC-4, rickman wrote:
> >> On 4/5/2016 3:15 PM, Rick C. Hodgin wrote:
> >>> I have a desire to create an 80386 CPU in FPGA form, one which will plug in
> >>> to the 132-pin socket of existing 80386 motherboard as a replacement CPU.  I
> >>> want to be able to provide the features of the 80386 on that machine, but
> >>> through my FPGA, to then allow me to extend the ISA to include other
> >>> instructions and abilities.
> >>>
> >>> Does anybody have an experience or advice in creating an FPGA-based CPU that
> >>> connects to a real hardware device and simulates the real device's abilities?
> >>>
> >>> For example, the 80386 uses 5V and the Altera board I have drives 1.xV and
> >>> 3.3V max, so I'd have to use a level converter.  At speeds up to a max of
> >>> 40 MHz, would there be any issues?
> >>
> >> Even at 40 MHz you will need to be tidy with your routing to keep the
> >> signals from ringing, etc.
> >
> > If I can get the machine underclocked, I'd like to bring it down into the
> > low KHz or even Hz range if possible, but something 100 KHz or lower at
> > least.
> 
> Running with a slow clock doesn't assure a lack of problems from edge 
> rates.  The edges usually are still just as fast and that is what 
> creates problems.
> 
> 
> > I envision the Cyclone V GX being mounted a couple inches above the 80386
> > socket.  I would use the HSMC to GPIO port to connect to the CPU socket.
> 
> I don't know about the HSMC port, but I don't think you need anything 
> special for a 40 MHz interface.
> 
> 
> > I had considered at first using the co-processor socket and emulating the
> > 80387 ISA at first.  I may still do that, but regardless, there are only
> > 90 pins that are active on the 80386, and 64 of those are direct address
> > and data pins, with another 20 being control pins for when those lines
> > are active, and in what mode they're active.
> >
> > There really isn't much logic involved in hooking up an 80386, which is
> > why I'm attempting this project.
> >
> > To be honest, I wouldn't even mind dipping back down to a 4.77 MHz 8086
> > system and starting there as part of the ISA I'll support for the 80386
> > contains a full 8086 subset.
> >
> >> I don't know the details of the 386 chip I/O
> >> specs, but quickswitch type parts will do a good job of level shifting
> >> between 3.33 and 5 volts without adding much delay.  Because the signal
> >> passes between the source and drain there is very little delay.  They
> >> don't pull up to 5 volts, but 5 volt logic usually only need 2.x volts
> >> anyway.  But you'll need to check the parts you are interfacing to on
> >> the mother board or just give it a wing.  You can add pullups on the 5
> >> volt side, but pullups tend to be slow.  Even a few ns of added delay
> >> can cause a 386 not to work.  Many of the early mobos had timing issues
> >> because of the TTL logic used.
> >
> > Excellent information, thank you.
> >
> >> I don't think 386 mobos had chip sets in place of the TTL, did they?
> >
> > Not originally, but later on.  These motherboards were manufactured in
> > the early 90s, and came with Am386 CPUs manufactured in 91 or 92.  I
> > believe the boards I have had switched to chip sets by then.
> 
> I recall that because there was no "standard" for the design of the 
> motherboard other than what IBM had done, there were some differences 
> between the various chip sets.  In those days they *were* chip sets as 
> the whole shebang didn't end up in one chip like was used later and 
> still called a "chip set".  lol
> 
> 
> >>> Also, I'd like to create a "monitor board," which is a board with a 132-
> >>> pin male socket connecting to the CPU on one side, and a 132-pin female
> >>> socket on the other side to which a real 80386 CPU would connect, and then
> >>> to be able to pull signals off the wires between the CPU socket and the
> >>> CPU itself.  I had assumed I would use opto-isolation for this, but I don't
> >>> know if it would work or be best.
> >>
> >> Opto-isolation is pretty slow compared to 40 MHz, but maybe there are
> >> faster converters these days.  Why do you need isolation?
> >
> > I may not need it.  However, when I was working on stepper motors back
> > in the mid-90s, I believe we used them to maintain a low power draw on
> > the circuits we were monitoring.
> 
> Optos are the opposite of low power draw on busses.  Enough current is 
> required to drive an LED on the sensing side.  Optos are typically used 
> to provide isolation from circuits that can have ground swings or 
> otherwise be noisy or have high voltage spikes, like motor circuits.
> 
> 
> >>> In addition, and specific to the 80386 CPU, AMD manufactured an Am386 CPU
> >>> that is 100% compatible with the Intel 80386, but it has the ability to
> >>> underclock down to even 0 MHz in a standby mode (allowing it to consume
> >>> only 0.001 Watts).  I'm wondering if anyone has any experience underclocking
> >>> an 80386 motherboard down into the KHz range, or even Hz range, and if it
> >>> would still work at those slow speeds on the board?
> >>
> >> No experience, but the parts that would give trouble at slow clocks were
> >> the NMOS devices that went out long before the 386.  Certainly TTL and
> >> CMOS don't normally have a problem with slow clocking.
> >
> >  From what I've read, Intel's 80386 CPUs would not clock below 10 MHz well.
> > But AMD's would clock down to any clock speed including 0 MHz.  It's why
> > I've wanted to try to target these systems which came with the Am386 CPU,
> > for their underclocking abilities.
> 
> I've forgotten more than I knew, lol.  That may be accurate.  I know the 
> original NMOS circuits used dynamic circuits where values were 
> remembered on capacitance and so had minimum clock rates.  Maybe even on 
> CMOS designs they did the same thing.
> 
> 
> >>> My goals in slowing down the CPU are to detect and isolate timing protocols,
> >>> which I can then scale up to higher speeds once identified.
> >>>
> >>> In any event, any help or advice is appreciated.  Thank you.
> >>
> >> I have a book somewhere on the ISA bus with timing info.  ISA was never
> >> fully specified.  I think there was an effort to produce a spec, but it
> >> got canned and retracted at some point.  You can't even find draft
> >> versions of it now.  But that was more of an 8086/80286 thing.  I'm not
> >> sure the ISA bus was still mapped directly to the 386 bus.  I just don't
> >> remember.
> >
> > IIRC, it operated at 4.77 MHz for 8-bit bus, and 6 MHz or 8 MHz for the
> > 16-bit bus.  I don't know if that speed is required, or if it's the
> > standard clock speed when the system was operating at its normal clock
> > speed as would be setup by early BIOS during boot. I assume once it boots
> > up, the entire system can be overclocked or underclocked by altering the
> > frequency emitted by the clock circuit, and the whole system would rise
> > and fall in relative speed parity.  Just a guess though.
> 
> It's not actually a synchronous bus.  Everything is timed by the read 
> and write strobes with some other signals helping to control data 
> directions on buffers.  It started with the 8088 I/O bus controls and 
> remained compatible I believe, but I'm not sure.  If you don't mind 
> stretching the cycles a bit it can be run synchronously.  I'll see if I 
> can find that book.
> 
> -- 
> 
> Rick

Alright ... suppose I target this from another angle.  What if I take
the CPU completely off the 80386 motherboard, and create a custom socket
connected to my FPGA, and I provide it with everything it requires?

The Am386 CPUs operated at speeds from 0 MHz to 40 MHz.  Since they can
actually clock at any speed, I could take the CPU completely away from the peculiar and bizarre 80386 motherboard design, and instead provide the
facilities which basically allow the FPGA to be its motherboard, feeding
it whatever it's required.

Possible?

BTW, if I haven't said so you, I greatly appreciate your assistance and
advice.  It is very kind of you to help me in this way, and much, very
much appreciated.

Best regards,
Rick C. Hodgin

On 4/5/2016 10:47 PM, Rick C. Hodgin wrote:
>
> Alright ... suppose I target this from another angle.  What if I take
> the CPU completely off the 80386 motherboard, and create a custom socket
> connected to my FPGA, and I provide it with everything it requires?
>
> The Am386 CPUs operated at speeds from 0 MHz to 40 MHz.  Since they can
> actually clock at any speed, I could take the CPU completely away from the peculiar and bizarre 80386 motherboard design, and instead provide the
> facilities which basically allow the FPGA to be its motherboard, feeding
> it whatever it's required.
>
> Possible?

Sure.  Booting one of these things may be a bit complicated, but not 
likely any worse than booting a modern high end ARM processor.  Likely a 
lot easier.


> BTW, if I haven't said so you, I greatly appreciate your assistance and
> advice.  It is very kind of you to help me in this way, and much, very
> much appreciated.

No problem.  This an interesting if not mysterious project.

-- 

Rick

On 05/04/16 21:15, Rick C. Hodgin wrote:
> I have a desire to create an 80386 CPU in FPGA form, one which will plug in
> to the 132-pin socket of existing 80386 motherboard as a replacement CPU.  I
> want to be able to provide the features of the 80386 on that machine, but
> through my FPGA, to then allow me to extend the ISA to include other
> instructions and abilities.
>
> Does anybody have an experience or advice in creating an FPGA-based CPU that
> connects to a real hardware device and simulates the real device's abilities?
>
> For example, the 80386 uses 5V and the Altera board I have drives 1.xV and
> 3.3V max, so I'd have to use a level converter.  At speeds up to a max of
> 40 MHz, would there be any issues?
>
> Also, I'd like to create a "monitor board," which is a board with a 132-
> pin male socket connecting to the CPU on one side, and a 132-pin female
> socket on the other side to which a real 80386 CPU would connect, and then
> to be able to pull signals off the wires between the CPU socket and the
> CPU itself.  I had assumed I would use opto-isolation for this, but I don't
> know if it would work or be best.
>
> In addition, and specific to the 80386 CPU, AMD manufactured an Am386 CPU
> that is 100% compatible with the Intel 80386, but it has the ability to
> underclock down to even 0 MHz in a standby mode (allowing it to consume
> only 0.001 Watts).  I'm wondering if anyone has any experience underclocking
> an 80386 motherboard down into the KHz range, or even Hz range, and if it
> would still work at those slow speeds on the board?
>
> My goals in slowing down the CPU are to detect and isolate timing protocols,
> which I can then scale up to higher speeds once identified.
>
> In any event, any help or advice is appreciated.  Thank you.
>
> Best regards,
> Rick C. Hodgin
>

If you plan to slow down the CPU by slowing down the FPGA clock be 
careful: FPGAs like clean and relatively fast edges and some slow 
generators don't work well.

Pere

On Wednesday, April 6, 2016 at 12:35:43 AM UTC-4, rickman wrote:
> On 4/5/2016 10:47 PM, Rick C. Hodgin wrote:
> >
> > Alright ... suppose I target this from another angle.  What if I take
> > the CPU completely off the 80386 motherboard, and create a custom socket
> > connected to my FPGA, and I provide it with everything it requires?
> >
> > The Am386 CPUs operated at speeds from 0 MHz to 40 MHz.  Since they can
> > actually clock at any speed, I could take the CPU completely away from the peculiar and bizarre 80386 motherboard design, and instead provide the
> > facilities which basically allow the FPGA to be its motherboard, feeding
> > it whatever it's required.
> >
> > Possible?
> 
> Sure.  Booting one of these things may be a bit complicated, but not 
> likely any worse than booting a modern high end ARM processor.  Likely a 
> lot easier.

Agreed.  The 80386 manuals document the power-on state, and provided I
setup the SRAM emulation to point to the correct addresses with proper
80386 binary code, it should start processing away like gangbusters. :-)

My next step is to construct the board that has the 132-pin socket, and
the mated ports for the GPIO cables that the HSMC-to-GPIO board has.

Do you have any particular recommendation as to where I should go to get
the board manufactured?  I've seen a host of online services where you
either use their tools, or provide a black-and-white bitmap for each
layer outlining the vias, pin locations, and wires, along with scaling
info.

> > BTW, if I haven't said so you, I greatly appreciate your assistance and
> > advice.  It is very kind of you to help me in this way, and much, very
> > much appreciated.
> 
> No problem.  This an interesting if not mysterious project.

:-)  I don't want to spend a lot of time trying to get it to work, but if
I can, it would be really nice to be able to have my CPU side-by-side with
a real-world product, able to test out compatibility.

And if it works, then for my ARM-based ISA, I would do something similar
with a slower ARM core, something also around 32 MHz or so.

Best regards,
Rick C. Hodgin

On Wednesday, April 6, 2016 at 8:16:26 AM UTC-4, o pere o wrote:
> If you plan to slow down the CPU by slowing down the FPGA clock be 
> careful: FPGAs like clean and relatively fast edges and some slow 
> generators don't work well.

I plan on using the FPGA clock as it is, and then creating logic within
the FPGA to drive a pin high and low which produces the simulated clock
signal at a speed I can vary.

Since the Am386 can operate at a wide range of frequencies, I'll start
out at a 2 Hz clock and see what happens. :-)

Best regards,
Rick C. Hodgin