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Using an FPGA to drive the 80386 CPU on a real motherboard

Started by Rick C. Hodgin April 5, 2016
On Wednesday, April 6, 2016 at 5:45:12 PM UTC-4, Rick C. Hodgin wrote:
> I figured the CPUs I'd make would cost $1,000 each in the early samples, > with an anticipated 50 to 100 CPU minimum, but that if I am able to create > the industry I'm hoping to create (people who are willing to buy CPUs that > are wrought of love, more than high-speed bells and whistles, looking to > them as a utility to augment man's existence, rather than as a whizz bang > eye candy newest fad ("gotta have the $12K iPhone 6 because my $10K iPhone > 5 is just so last year") kind of thing).
...then the need for larger runs would be there and the price would go down. Best regards, Rick C. Hodgin
Rick C. Hodgin wrote:


> > I figured the CPUs I'd make would cost $1,000 each in the early samples,
OK, the MOSIS standard order is for 40 parts. So, that's $40K each revision. Unless you are truly brilliant, it is going to take a BUNCH of respins of the part to get anything working.
> with an anticipated 50 to 100 CPU minimum, but that if I am able to create > the industry I'm hoping to create (people who are willing to buy CPUs that > are wrought of love, more than high-speed bells and whistles, looking to > them as a utility to augment man's existence, rather than as a whizz bang > eye candy newest fad ("gotta have the $12K iPhone 6 because my $10K iPhone > 5 is just so last year") kind of thing).
Uhhh, I can imagine there will be at LEAST 5 customers for this. How many shirts do you have? Because you are certainly going to lose your shirt on this project! Jon
On 4/6/2016 5:05 PM, Jon Elson wrote:
> rickman wrote: > > >> I like some of the Lattice chips because they have Flash. Once you >> program them the programmer is no longer needed. If you are going to >> use a RAM configured part you need something to program the FPGA every >> time you power it up, so might as well design an MCU programmer onto >> your board. >> > Xilinx also has he Spartan 3AN (N for non-volatile). For a couple extra > bucks, you can get get the flash memory built in. Otherwise, their Spartan > 3 family will download from a fariety of serial PROMS with no additional > circuitry. I've been using SST serial EPROMS for some time, they are > something like $0.80 which seems pretty amazing. They don't make them in > DIP, however, so I have to make a little board about fingernail size so I > can plug them in to the board.
Serial flash parts use extra board space and are a PITA to design in so you can program on the board. The serial configuration of Xilinx parts is also rather slow in comparison to the boot time of a internal flash FPGA. I believe it is something like two orders of magnitude faster. The Spartan 3AN is a bit of a joke in some respects, but if you are using Xilinx parts I guess that is what you get. If it were a good idea, why do they only do that on the 10 year old Spartan 3A line? -- Rick
On 4/6/2016 4:41 PM, Rick C. Hodgin wrote:
> On Wednesday, April 6, 2016 at 4:38:20 PM UTC-4, rickman wrote: >> On 4/6/2016 4:19 PM, Rick C. Hodgin wrote: >>> On Wednesday, April 6, 2016 at 3:00:51 PM UTC-4, Aleksandar Kuktin wrote: >>>> On Wed, 06 Apr 2016 11:51:15 -0400, rickman wrote: >>>> >>>>> On 4/6/2016 8:20 AM, Rick C. Hodgin wrote: >>>>>> On Wednesday, April 6, 2016 at 12:35:43 AM UTC-4, rickman wrote: >>>>>>> On 4/5/2016 10:47 PM, Rick C. Hodgin wrote: >>>>>>>> >>>>>>>> Alright ... suppose I target this from another angle. What if I take >>>>>>>> the CPU completely off the 80386 motherboard, and create a custom >>>>>>>> socket connected to my FPGA, and I provide it with everything it >>>>>>>> requires? >>>> >>>> This is probably a much better idea. >>>> >>>> The reason for that is that I would expect the motherboard manufacturer >>>> probably didn't expect someone would be messing with the onboard clock. >>>> And then they, presumably, didn't design it to handle it. It's enough for >>>> a single component to misbehave at low frequency and the whole thing >>>> would fail. >>>> >>>> Doing things the other way around should be easier. I can't imagine the >>>> CPU to be that picky about what it gets from the outside world. >>>> >>>> Then again... if the memory controller is embedded in the CPU... >>> >>> Not on the 386 chips. The first memory controllers which appeared on >>> x86 CPUs came from AMD and that was on K8 I believe. >>> >>>>> You should be able to design one board with an FPGA, a 386 socket and a >>>>> 386 plug which will work for any of the three things you have talked >>>>> about doing, emulating the mobo with your FPGA, emulating the 386 with >>>>> your FPGA and monitoring the 386 in a real mobo with the FPGA. >>>>> >>>>> 386 Chip >>>>> ____________ >>>>> ++++++++++++ FPGA >>>>> ============== _____________ >>>>> |||||||||||| ,,,,,,,,,,,,, >>>>> =================================================== PCB >>>>> |||||||||||| >>>>> Plugs into 386 Mobo >>>>> >>>>> When emulating the 386 unplug it from the socket. When emulating the >>>>> mobo, unplug from the mobo. When monitoring the 386 in operation plug >>>>> in the 386 and plug the board into the mobo. >>>> >>>> Oh, ok. I was really struggling to figure out how would he mechanically >>>> intercept the signals between the CPU and the motherboard. Although this >>>> design still has me scratching my head about those several hundred pins >>>> that need to be manufactured and installed (by hand?), it's much better >>>> than what I envisioned. :) >>>> >>>> If you two really build such a PCB, would you post the design here? I'd >>>> really like to see how you route all those wires. :) >>> >>> The 80386 used a 132-pin socket, of which 40 pins are either not connected >>> or only carry Vcc or Vss voltages: >>> >>> http://www.electronicsurplus.com/samtec-ndas-132zsgt-h-connectors-ic-sockets-132-pin-grid-array-package-of-2 >>> >>> The sockets and pinouts are fairly standard, though less common these >>> days. I could de-solder a connector on one of the motherboards I have >>> for my particular application. Provided the vias were all in the right >>> place, it should transfer over and re-solder just fine. >>> >>>> An innocent question: why not intercept the signals running at full >>>> speed, storing them and transmitting them later? You probably wouldn't be >>>> able to record a whole lot of them at once, but you record a bit, power >>>> cycle the CPU, record a bit more, power cycle the CPU, record a bit >>>> more.... >>> >>> That was my first desire. But, once I learned about AMD's Am386's >>> ability to clock down to even 0 MHz and maintain its internal state >>> correctly, I began to think it would be easier to examine if it were >>> running at lower speed. >>> >>> The clock signal to an 80386 is double-pumped, so a 2 Hz input clock >>> would cause 1 clock cycle per second. >> >> That jogged a recollection. Once the internal speeds got faster they >> added phase locked loops to use a slow external clock and a faster >> internal clock. These are no longer compatible with slow clocking. > > I believe that occurred on the 80486 and the DX/2, DX/3 (un-released), > and DX/4 models. > > The 80387 co-processor has the ability to run dual clocks internally, > which are governed in the range of 14:10 (I believe), but they don't > have to run faster. They can be locked and always run at the same > speed. > >> Same is true of FPGAs if you use the internal PLL. It will be fairly >> simple to generate a variable speed clock to drive the CPU with. Then >> the FPGA can either work at that same rate, or resync the interface to a >> fast internal clock which does not change rate. It all depends on what >> you are doing with the data once you get it and what your other >> interfaces are. > > I had the idea that I would use the simulated clock output for an input > trigger back into the FPGA for doing all monitoring/sampling.
If you are plugged into the mobo, I don't think you can source the clock. That would work ok if the FPGA is emulating the mobo. -- Rick
On 4/6/2016 4:38 PM, Rick C. Hodgin wrote:
> On Wednesday, April 6, 2016 at 3:07:55 PM UTC-4, Aleksandar Kuktin wrote: >> On Tue, 05 Apr 2016 12:15:35 -0700, Rick C. Hodgin wrote: >> >>> I have a desire to create an 80386 CPU in FPGA form, one which will plug >>> in to the 132-pin socket of existing 80386 motherboard as a replacement >>> CPU. >> >> Okay, so I'm not the only one who's into slow system design. :) > > I am not objected to having it go faster, but the faster it goes the > most expensive it is. :-) > > Okay, are you sitting down? Here goes... :-) > > My ultimate goal is to build a completely homemade CPU using my own > garage fab on 3 to 10 micron processes! Once I can get that product > working, then it can be optimized and honed to more modern processes, > with my ultimate goal coming in around those process technologies used > in the late 90s around 500 nm. > >>> I want to be able to provide the features of the 80386 on that >>> machine, but through my FPGA, to then allow me to extend the ISA to >>> include other instructions and abilities. >> >> I have to ask: why spend time hacking x86 when there are so many other, >> BETTER architectures out there? :) > > I have a long history on 80386. I wrote my own kernel, debuggers, etc. > It's been a relationship dating back to the late 80s. > > However, one of the reasons I'm doing this is because I am extending > the ISA out to include 40-bit addresses, rather than just 32-bit, > which accesses memory in the Terabyte range, and to include a built-in > ARM ISA which allows the CPU to switch between ISAs based on branch > instructions. > >> Also, why are you doing this? Is this a hobby? Work related? Starting a >> new bussiness? Want to design and implement a NSA-proof PC? > > To be honest, I am a Christian, and I want to use the talents I was gifted > with and give the fruit of my labor back to God, and to my fellow man (and > not a pursuit of money, or proprietary IP, or patents, or other such things, > but rather an expression of love basically in giving back).
How would this accomplish that, the benefit to God or man?
>>> Does anybody have an experience or advice in creating an FPGA-based CPU >>> that connects to a real hardware device and simulates the real device's >>> abilities? >> >> Does simulation count? :D > > Yes. Also in emulation, as by a real FPGA product, but one which does not > plug into a socket, but is its own entire creation. Here's an Aleksander > who created a 486 SX CPU (it has not integrated FPU): > > https://github.com/alfikpl/ao486 > > My goals are part of a project I'm working on called LibSF 386-x40, which > is a 40-bit extension to the 80386, and 32-bit ARM. I use a WEX register > model which extends the 32-bit registers to 40-bit registers: > > https://github.com/RickCHodgin/libsf/blob/master/li386/li386-documentation/images/wex_register_mapping.png > > However, in the past couple weeks I've had the idea of a pointer selector, > which operates like a segment selector, but on a specific pointer register. > When enabled, it loads an extra 8-bits into the segment register associated > with specific register, such that it then is able to reference a 4GB window > of memory within the 1 TB address space: > > https://groups.google.com/d/msg/comp.arch/bcpb03mL0o0/xUBzCXDmBgAJ > > These are all part of long-term plans. I'd like to have my first CPU being > shipped to a fab for real manufacturing by July 12, 2022, which I expect to > be around a 90 MHz part.
So in 2022 this will rival the $5 ARM MCU devices currently available? -- Rick
On 4/6/2016 11:40 PM, Jon Elson wrote:
> Rick C. Hodgin wrote: > > >> >> I figured the CPUs I'd make would cost $1,000 each in the early samples, > OK, the MOSIS standard order is for 40 parts. So, that's $40K each > revision. Unless you are truly brilliant, it is going to take a BUNCH of > respins of the part to get anything working. >> with an anticipated 50 to 100 CPU minimum, but that if I am able to create >> the industry I'm hoping to create (people who are willing to buy CPUs that >> are wrought of love, more than high-speed bells and whistles, looking to >> them as a utility to augment man's existence, rather than as a whizz bang >> eye candy newest fad ("gotta have the $12K iPhone 6 because my $10K iPhone >> 5 is just so last year") kind of thing). > > Uhhh, I can imagine there will be at LEAST 5 customers for this. How many > shirts do you have? Because you are certainly going to lose your shirt on > this project!
I think Rick H doesn't understand that electronics works exactly the way it does because it allows the industry to provide $25 cell phones to those who *need* them rather than the $400 latest eye candy phones to those who want them. (I don't know of any $12,000 phones) In some ways the $400 phones subsidize the cheap phones, but not in a serious way. The expensive phones just drive the "bleeding edge" market since that always costs more initially. Then once the high initial costs are amortized, the rest of us get the benefit of the technology at the sustained product rate. Producing a CPU chip with no real market in an antique technology will not help anyone, man or God. This project *is* starting to sound familiar now. -- Rick
On 4/6/2016 4:38 PM, Rick C. Hodgin wrote:
> On Wednesday, April 6, 2016 at 3:07:55 PM UTC-4, Aleksandar Kuktin wrote: > >> Also, why are you doing this? Is this a hobby? Work related? Starting a >> new bussiness? Want to design and implement a NSA-proof PC? > > To be honest, I am a Christian, and I want to use the talents I was gifted > with and give the fruit of my labor back to God, and to my fellow man (and > not a pursuit of money, or proprietary IP, or patents, or other such things, > but rather an expression of love basically in giving back).
This jogged a memory of a joke I was told at work when I worked on an IRAD project that was being graded by the government. The government format for the write up had a few sections and two were the GOAL and the PURPOSE. Everyone was confused about the difference in the two. So Fred wrote his report and said his goal was to measure some parameter and his purpose was to prove the parameter met some requirements. His boss read his report and said, "No, your goal is to prove the parameter met the requirements so what is your purpose?". He worked on it again saying his purpose was to show the unit X would work in system Y. It was reviewed by his second level boss who said, "No, your goal is to prove unit X works in system Y, what is your purpose?" This happened a couple more times until his report got through all the reviewers and he presented his report to a meeting. He started out saying... "My purpose is to get into heaven". -- Rick
On Wednesday, April 6, 2016 at 11:40:35 PM UTC-4, Jon Elson wrote:
> Rick C. Hodgin wrote: > > > > > > I figured the CPUs I'd make would cost $1,000 each in the early samples, > OK, the MOSIS standard order is for 40 parts. So, that's $40K each > revision. Unless you are truly brilliant, it is going to take a BUNCH of > respins of the part to get anything working.
I can't remember who it was I searched a while back (2014 I think), but I found a company that was manufacturing on 250nm and 500nm process technologies. The mask sets were $15K each, and each run varied, but the total cost for 100 parts was less than $100K including masks.
> > with an anticipated 50 to 100 CPU minimum, but that if I am able to create > > the industry I'm hoping to create (people who are willing to buy CPUs that > > are wrought of love, more than high-speed bells and whistles, looking to > > them as a utility to augment man's existence, rather than as a whizz bang > > eye candy newest fad ("gotta have the $12K iPhone 6 because my $10K iPhone > > 5 is just so last year") kind of thing). > > Uhhh, I can imagine there will be at LEAST 5 customers for this. How many > shirts do you have? Because you are certainly going to lose your shirt on > this project!
Well, it's not a goal. It's not being done for money. I would like to have assistance from those who are willing to give. I also don't intend on being the only one who works on it. I intend others who are experts in this field will come forward and help out. And if not, then I will do my best. Best regards, Rick C. Hodgin
On Thursday, April 7, 2016 at 2:42:24 AM UTC-4, rickman wrote:
> On 4/6/2016 4:41 PM, Rick C. Hodgin wrote: > > On Wednesday, April 6, 2016 at 4:38:20 PM UTC-4, rickman wrote: > >> On 4/6/2016 4:19 PM, Rick C. Hodgin wrote: > >>> On Wednesday, April 6, 2016 at 3:00:51 PM UTC-4, Aleksandar Kuktin wrote: > >>>> On Wed, 06 Apr 2016 11:51:15 -0400, rickman wrote: > >>>> > >>>>> On 4/6/2016 8:20 AM, Rick C. Hodgin wrote: > >>>>>> On Wednesday, April 6, 2016 at 12:35:43 AM UTC-4, rickman wrote: > >>>>>>> On 4/5/2016 10:47 PM, Rick C. Hodgin wrote: > >>>>>>>> > >>>>>>>> Alright ... suppose I target this from another angle. What if I take > >>>>>>>> the CPU completely off the 80386 motherboard, and create a custom > >>>>>>>> socket connected to my FPGA, and I provide it with everything it > >>>>>>>> requires? > >>>> > >>>> This is probably a much better idea. > >>>> > >>>> The reason for that is that I would expect the motherboard manufacturer > >>>> probably didn't expect someone would be messing with the onboard clock. > >>>> And then they, presumably, didn't design it to handle it. It's enough for > >>>> a single component to misbehave at low frequency and the whole thing > >>>> would fail. > >>>> > >>>> Doing things the other way around should be easier. I can't imagine the > >>>> CPU to be that picky about what it gets from the outside world. > >>>> > >>>> Then again... if the memory controller is embedded in the CPU... > >>> > >>> Not on the 386 chips. The first memory controllers which appeared on > >>> x86 CPUs came from AMD and that was on K8 I believe. > >>> > >>>>> You should be able to design one board with an FPGA, a 386 socket and a > >>>>> 386 plug which will work for any of the three things you have talked > >>>>> about doing, emulating the mobo with your FPGA, emulating the 386 with > >>>>> your FPGA and monitoring the 386 in a real mobo with the FPGA. > >>>>> > >>>>> 386 Chip > >>>>> ____________ > >>>>> ++++++++++++ FPGA > >>>>> ============== _____________ > >>>>> |||||||||||| ,,,,,,,,,,,,, > >>>>> =================================================== PCB > >>>>> |||||||||||| > >>>>> Plugs into 386 Mobo > >>>>> > >>>>> When emulating the 386 unplug it from the socket. When emulating the > >>>>> mobo, unplug from the mobo. When monitoring the 386 in operation plug > >>>>> in the 386 and plug the board into the mobo. > >>>> > >>>> Oh, ok. I was really struggling to figure out how would he mechanically > >>>> intercept the signals between the CPU and the motherboard. Although this > >>>> design still has me scratching my head about those several hundred pins > >>>> that need to be manufactured and installed (by hand?), it's much better > >>>> than what I envisioned. :) > >>>> > >>>> If you two really build such a PCB, would you post the design here? I'd > >>>> really like to see how you route all those wires. :) > >>> > >>> The 80386 used a 132-pin socket, of which 40 pins are either not connected > >>> or only carry Vcc or Vss voltages: > >>> > >>> http://www.electronicsurplus.com/samtec-ndas-132zsgt-h-connectors-ic-sockets-132-pin-grid-array-package-of-2 > >>> > >>> The sockets and pinouts are fairly standard, though less common these > >>> days. I could de-solder a connector on one of the motherboards I have > >>> for my particular application. Provided the vias were all in the right > >>> place, it should transfer over and re-solder just fine. > >>> > >>>> An innocent question: why not intercept the signals running at full > >>>> speed, storing them and transmitting them later? You probably wouldn't be > >>>> able to record a whole lot of them at once, but you record a bit, power > >>>> cycle the CPU, record a bit more, power cycle the CPU, record a bit > >>>> more.... > >>> > >>> That was my first desire. But, once I learned about AMD's Am386's > >>> ability to clock down to even 0 MHz and maintain its internal state > >>> correctly, I began to think it would be easier to examine if it were > >>> running at lower speed. > >>> > >>> The clock signal to an 80386 is double-pumped, so a 2 Hz input clock > >>> would cause 1 clock cycle per second. > >> > >> That jogged a recollection. Once the internal speeds got faster they > >> added phase locked loops to use a slow external clock and a faster > >> internal clock. These are no longer compatible with slow clocking. > > > > I believe that occurred on the 80486 and the DX/2, DX/3 (un-released), > > and DX/4 models. > > > > The 80387 co-processor has the ability to run dual clocks internally, > > which are governed in the range of 14:10 (I believe), but they don't > > have to run faster. They can be locked and always run at the same > > speed. > > > >> Same is true of FPGAs if you use the internal PLL. It will be fairly > >> simple to generate a variable speed clock to drive the CPU with. Then > >> the FPGA can either work at that same rate, or resync the interface to a > >> fast internal clock which does not change rate. It all depends on what > >> you are doing with the data once you get it and what your other > >> interfaces are. > > > > I had the idea that I would use the simulated clock output for an input > > trigger back into the FPGA for doing all monitoring/sampling. > > If you are plugged into the mobo, I don't think you can source the > clock. That would work ok if the FPGA is emulating the mobo.
Correct. I don't plan on connecting to the motherboard though until I get the entire ISA working. And even then it will be a minimal research effort such that if I can't get it working in a week or two, then I'll move on to the next thing. After hearing all of the difficulties I may have on the motherboard side, the re-grouping of just working with the Am386 CPU makes a lot more sense. Plus, it actually accomplishes nearly all of my goals as my goals were to replace the CPU's instruction set with my own, and to validate it 1:1 that I am correct. By having a side-by-side comparison I can do that. And as I've stated, it might even be interesting to try to get other 80386-clone CPUs to test out side-by-side in the configuration, and then write a paper outlining where they are different. But, that's the lowest possible goal, just a "wouldn't it be interesting" thought. :-) Best regards, Rick C. Hodgin
On Thursday, April 7, 2016 at 2:46:51 AM UTC-4, rickman wrote:
> On 4/6/2016 4:38 PM, Rick C. Hodgin wrote: > > On Wednesday, April 6, 2016 at 3:07:55 PM UTC-4, Aleksandar Kuktin wrote: > >> Also, why are you doing this? Is this a hobby? Work related? Starting a > >> new bussiness? Want to design and implement a NSA-proof PC? > > > > To be honest, I am a Christian, and I want to use the talents I was gifted > > with and give the fruit of my labor back to God, and to my fellow man (and > > not a pursuit of money, or proprietary IP, or patents, or other such things, > > but rather an expression of love basically in giving back). > > How would this accomplish that, the benefit to God or man?
Well, it's difficult to describe to many people. To date, only a small handful have seen any value in the idea whatsoever ... but, some do see the value and I am one of them. :-) It comes down to our fundamental reason for being alive in this world. Am I a self-made man with all of my abilities being my abilities? Or do I acknowledge that I was gifted with those abilities by God, and then do I hold God in that place in my life ahead of all things? I am not rich. I am not strong. I am not many things. What I am though He has gifted me with. I happen to have an interest in these areas and, despite not having a formal education, have discovered over time that these things just make sense to me and I'm able to maneuver in them with little difficulty. They are also a great interest to me. So, I refocus the purposes of my life from within that knowledge and understanding: I was created by God. God had a purpose in creating me. I desire to do these things in my life, so I will do them for God. And if God has another purpose for me in my life, then as I am walking on this path, He will put up obstacles and roadblocks to move me from this direction to some other direction, which is the one He truly wanted me to be on. So long as I'm moving, and doing so for Him, I'm walking as I should. And for me, it's in this industry (hardware, and software). But for others walking similarly in their line of work, it would be in whatever they do, using whatever skills they possess. ----- It's an endeavor I've been working on since July 12, 2012, when I had instead started heading down a path of doing what I'm doing now on this project, except for GNU and the FSF. However, just before I began, I found out some things about Richard Stallman that were very disturbing to me, and I resolved within myself that I could not work for that entity, contributing to its growth or prosperity because its very foundations were wrought of a man whose viewpoints on several things are not only against God, but against most people's assessment of what is true right and true wrong. So, instead of the Free Software Foundation, I created the Liberty Software Foundation, and dedicated all of my work to honoring God. I have given the labor I possess on these projects away, so that others might benefit from them. I have done my best on this project, and not many others have seen benefit in my work, and I've observed a similar reaction to my efforts as I see here, where people initially are very interested in helping, but once they see any kind of an association with God, or doing work for God, there is a recoil, and a pulling away. Of course it makes me sad because I desire to create these hardware and software products, and I desire to receive help from others, but I also desire to do it in a way which gives God the credit (glory, honor, praise) for what He first did in me, giving me the abilities to do any of these things in the first place, and in all who participate as well. In essence, my heart cries out to God in acknowledgement of who He is, what He has done, and I recognize why we are here in our various short- comings, ineptitudes, strengths, and abilities: to help one another. We are here to compensate for one another's weaknesses, to be strong in areas they're weak, and have others be strong in the areas we're weak. And in these areas of hardware and software design, I would very much like to have a part running at 4 GHz or faster, but I cannot do that alone. My goals are more modest, though my hope remains that I will not only have a part running at 4 GHz, but rather that God will shine the light of knowledge and understanding in these areas of physics and allow a part to be created which operates at 100 GHz or faster, and does so on less power, less heat, etc. I am confident in my relationship with God, and with who God is, so I seek to do the things I do in my life for Him. I do this in my work, my hardware and software pursuits, in my family relationships, in the relationships I have/attempt with friends, etc. I make Him part of my life, and explicitly the biggest part, and the part out front of the things I do, and I do this because of who He is, who I am, and what He's given me here in this world. Bottom line: I am not a self-made man. I need His help, guidance, and that of those around me. But I know that together, in acknowledgement of Him, there is nothing we cannot accomplish.
> >>> Does anybody have an experience or advice in creating an FPGA-based CPU > >>> that connects to a real hardware device and simulates the real device's > >>> abilities? > >> > >> Does simulation count? :D > > > > Yes. Also in emulation, as by a real FPGA product, but one which does not > > plug into a socket, but is its own entire creation. Here's an Aleksander > > who created a 486 SX CPU (it has not integrated FPU): > > > > https://github.com/alfikpl/ao486 > > > > My goals are part of a project I'm working on called LibSF 386-x40, which > > is a 40-bit extension to the 80386, and 32-bit ARM. I use a WEX register > > model which extends the 32-bit registers to 40-bit registers: > > > > https://github.com/RickCHodgin/libsf/blob/master/li386/li386-documentation/images/wex_register_mapping.png > > > > However, in the past couple weeks I've had the idea of a pointer selector, > > which operates like a segment selector, but on a specific pointer register. > > When enabled, it loads an extra 8-bits into the segment register associated > > with specific register, such that it then is able to reference a 4GB window > > of memory within the 1 TB address space: > > > > https://groups.google.com/d/msg/comp.arch/bcpb03mL0o0/xUBzCXDmBgAJ > > > > These are all part of long-term plans. I'd like to have my first CPU being > > shipped to a fab for real manufacturing by July 12, 2022, which I expect to > > be around a 90 MHz part. > > So in 2022 this will rival the $5 ARM MCU devices currently available?
The part I have planned today won't. But if more people come together, we can together create something that will exceed it. It just takes the willingness from within to work together, and the guidance of God guiding our hearts and minds in the right direction, for He is truth, and this universe is His creation. If there is anyone who can guide us on the direction we should go, it's Him. And I place my faith, hope, and trust in Him because of who He is. That being said, that doesn't mean I don't want to work with you on this project. You have exhibited incredible kindness, and I have been moved by it. I have these desires to pursue these hardware ends, and nothing about that has changed. The only thing that's different now than it was yesterday or the day before, is that now you know that I am desiring to do this as an effort given over to God, in honoring Him with the fruits of my life. I hope this won't be a stumbling block. I find your generosity of spirit refreshing, and your knowledge and experience desirable assets that you are willing to share so freely. It's made me happy actually. :-) Best regards, Rick C. Hodgin