Chris_S wrote:> > Looking at the Lattice parts, the Mach 4A3 or Mach 4000 would be > candidates. I like the 4000, but there is almost no stock in the supply > chain yet. Arrow has only a couple parts moving and Avnet has virtually > none. Does not seem to have many designs going with it yet. > > Another problem with the 4000 is lack of packages. I really need a PQ208 > but there are none in the 4000 at all. Very few choices and little or no > stock even on those. > > The 4A3 is a possibility. There are 10 times as many parts moving through > the dists and the family has 8 different devices with lots of packages. But > the Icc is much higher on that series than the 4000. The factory tells me > that the 4000 will be more expensive than the 4A as well. > > I guess if you want to design for the long term future it's probably best to > pick a new family like the 4000. But you never know until later if that new > family makes it or not in the market.Exactly which new families did not "make it" in the market? I don't see any reason to expect the LC4000 (which is what I believe you are calling Mach 4000) will not be here as long as any other PLD family. This is a sound part and has some very good features. As to price, I have gotten much better pricing on the Lattice parts than I have on the Xilinx CR ones. Once the size gets up a bit, the CR parts get very, very expensive. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
XPLA3 vs. MAX3000A
Started by ●July 2, 2003
Reply by ●July 5, 20032003-07-05
Reply by ●July 5, 20032003-07-05
rickman wrote:> > Jim Granville wrote: > > > > Not entirely - the new Lattice devices offer 5V tolerance, but they > > also spec 'no more than 32 IO' at a time. > > Strange spec, how does one IO 'know' the state of another ?! > > That is 64 IOs at once and each one sinks current. Seems the total > current sets the limit. I tried to get more detail on this to find a > way to use it with the PC/104 bus, but they kept telling me to consider > a different family.<snip> Where did you find the sink current info/value - from the FAE ? I get this info from their Data: #5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed. # #IIH 2 Input High Leakage Current # 3.6V < VIN = 5.5V, Tj = 105�C <= 20 �A # 3.6V < VIN = 5.5V, Tj = 130�C <= 50 �A So that does not look to me like a clamping diode, which is how some others get their '5V tolerance' (just add a resistor :) Still leaves open the question of why a finite limit on the NUMBER of IO's that can have > 3.6V applied. It sounds tempting to get a device, and take 65 IO's to > 3.6V, and watch what happens :)) -jg
Reply by ●July 5, 20032003-07-05
Jim Granville wrote:> > rickman wrote: > > > > Jim Granville wrote: > > > > > > Not entirely - the new Lattice devices offer 5V tolerance, but they > > > also spec 'no more than 32 IO' at a time. > > > Strange spec, how does one IO 'know' the state of another ?! > > > > That is 64 IOs at once and each one sinks current. Seems the total > > current sets the limit. I tried to get more detail on this to find a > > way to use it with the PC/104 bus, but they kept telling me to consider > > a different family. > <snip> > > Where did you find the sink current info/value - from the FAE ? > > I get this info from their Data: > > #5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed. > # > #IIH 2 Input High Leakage Current > # 3.6V < VIN = 5.5V, Tj = 105�C <= 20 �A > # 3.6V < VIN = 5.5V, Tj = 130�C <= 50 �A > > So that does not look to me like a clamping diode, which is how > some others get their '5V tolerance' (just add a resistor :) > > Still leaves open the question of why a finite limit on the > NUMBER of IO's that can have > 3.6V applied. > > It sounds tempting to get a device, and take 65 IO's to > 3.6V, and > watch what happens :))I was told this by both an FAE and support by email. I am sure both are just parroting whatever is the original source of the info. I could not get them to give me any more detail, such as what effect a series resistance or other source impedance would have on the spec. From the FAE... "You are correct, the 5512MB does have a limit of 64 IOs that can be driven above 3.6V. This is due to the leakage current that appears when an input is biased above VCCio. They need to keep the total amount of this leakage current below a certain number and that worked out to 64 IOs." From support... "The 64 IOs 5V restriction is a reliability requirement for EE9 technology to ensure that we meet oxide FIT rate requirement." You could do your own testing on a device, but how would you know that this will be consistant across future versions of the device? It is not at all uncommon for a company to alter their process while keeping the original published spec. Xilinx has discussed this recently on the SpartanXL. While they maintained all the publised specs (and improved some), anything that you have tested in the past may no longer function that way. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
Reply by ●July 5, 20032003-07-05
rickman wrote:> > Jim Granville wrote: > > > > rickman wrote: > > > > > > Jim Granville wrote: > > > > > > > > Not entirely - the new Lattice devices offer 5V tolerance, but they > > > > also spec 'no more than 32 IO' at a time. > > > > Strange spec, how does one IO 'know' the state of another ?! > > > > > > That is 64 IOs at once and each one sinks current. Seems the total > > > current sets the limit. I tried to get more detail on this to find a > > > way to use it with the PC/104 bus, but they kept telling me to consider > > > a different family. > > <snip> > > > > Where did you find the sink current info/value - from the FAE ? > > > > I get this info from their Data: > > > > #5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed. > > # > > #IIH 2 Input High Leakage Current > > # 3.6V < VIN = 5.5V, Tj = 105�C <= 20 �A > > # 3.6V < VIN = 5.5V, Tj = 130�C <= 50 �A > > > > So that does not look to me like a clamping diode, which is how > > some others get their '5V tolerance' (just add a resistor :) > > > > Still leaves open the question of why a finite limit on the > > NUMBER of IO's that can have > 3.6V applied. > > > > It sounds tempting to get a device, and take 65 IO's to > 3.6V, and > > watch what happens :)) > > I was told this by both an FAE and support by email. I am sure both are > just parroting whatever is the original source of the info. I could not > get them to give me any more detail, such as what effect a series > resistance or other source impedance would have on the spec. > > From the FAE... > "You are correct, the 5512MB does have a limit of 64 IOs that can be > driven above 3.6V. This is due to the leakage current that appears when > an input is biased above VCCio. They need to keep the total amount of > this leakage current below a certain number and that worked out to 64 > IOs." > > From support... > "The 64 IOs 5V restriction is a reliability requirement for EE9 > technology to ensure that we meet oxide FIT rate requirement." ><snip> Thanks - Now, that support reply makes sense, the first one is a mangled version of the second one. If it is actually an oxide stress FIT parameter, then the 64 is an arbitary number, and failures are related to IP * Time products. The Oxide stress FIT of a single IP is finite, with more IPs you just ramp the statistical chances of ONE having a failure. It would be nice if they published more info on this, like the voltage/FIT slope, and just what the actual FIT value is, so in design you can decide on additional clamping, or if other measures are needed. There are processs where the gate-oxide thickness can be varied across the die ( and even thresholds, within a gate oxide ), but perhaps they have not made it to PLDs yet ? -jg
Reply by ●July 7, 20032003-07-07
jesse jenkins wrote:><snip>> CoolRunner-II incorporates aspects of both the XPLA3 family and the > XC9500 family, in a 1.8V core technology (read: 0.18 micron). > I saw some concern about discontinuing CoolRunner-II, which is absurd. > It was just released in the last few months to full production and > cost Xilinx multi millions of dollars to create. To date, the XC9500 family > and its 3.3V XC9500XL, and 2.5V XC9500XV family are all alive > and doing very well! The low power XPLA3 and CoolRunner-II family > are also doing very well. If you have any doubts, you can start opening > up various PDAs, cellphones and digital cameras and see them in there!<snip> Do you have any comments on Chris's mention (FAE attributed IIRC) that there is a new Coolrunner soon to replace the CR2 ? - or is it more a complementary family, like the lattice 4000/5000 series ? - or just an urban myth ? -jg
Reply by ●July 7, 20032003-07-07
I have a problem with the word:" replace". When your wife has a second baby, that does not replace your firstborn. It may now get its undue share of attention, but the old one is still going to be around and be loved and be useful.. In a previous post I explained the different aspects of obsolescence. Yes, we are always working on new products that somehow are so much better (or cheaper) that they supplant the older parts for new designs, but in our product line-up hardly anything is ever being "replaced." Old PLDs never die, they just fade into obsolescence. Peter Alfke ============== Jim Granville wrote:> > > Do you have any comments on Chris's mention (FAE attributed IIRC) > that there is a new Coolrunner soon to replace the CR2 ? > - or is it more a complementary family, like the lattice 4000/5000 > series ? > - or just an urban myth ? > -jg
