Interfacing an 1GS ADC

Hi,

It's not the first time this question has been asked, but I'd like to
know todays state of art:
Are their any devices at Altera, Xilinx or others, capabable of
handling the fast throughput of high-speed ADCs (1 GS), such as
Atmel's AT84AD001B or NS ADC08D1000 ? Preferably without an external
DMUX-device...
Using the ADC's internal DEMUX leaves us with 16 500 MHz LVDS lines
per channel.

Thanks,

  Alex

On 6 Sep 2004 02:35:03 -0700, A_Ungerer@netcourrier.com (Alex) wrote:

>Hi,
>
>It's not the first time this question has been asked, but I'd like to
>know todays state of art:
>Are their any devices at Altera, Xilinx or others, capabable of
>handling the fast throughput of high-speed ADCs (1 GS), such as
>Atmel's AT84AD001B or NS ADC08D1000 ? Preferably without an external
>DMUX-device...
>Using the ADC's internal DEMUX leaves us with 16 500 MHz LVDS lines
>per channel.

500Mbps per LVDS pair doesn't sound too fast.  I'd be interested in
knowing whether there are any recent FPGAs that *can't* handle that
speed.

Xilinx XAPP622 shows how it can be done:
http://www.xilinx.com/bvdocs/appnotes/xapp622.pdf

Regards,
Allan

I did a design a couple years ago in a VirtexE-7 that interfaced to an
Atmel 1GHz 8 bit ADC.  IIRC, that ADC output 4 samples at a time (perhaps
there was a matching mux chip).  Once inside the FPGA the signal was
mixed and FFT'd.  The incoming sample rate was 960MHz.  So yes, the
answer is most current FPGAs can handle the throughput with some
clever/careful design.  The new crop of FPGAs are considerably faster
than the VirtexE devices.

Alex wrote:

> Hi,
>
> It's not the first time this question has been asked, but I'd like to
> know todays state of art:
> Are their any devices at Altera, Xilinx or others, capabable of
> handling the fast throughput of high-speed ADCs (1 GS), such as
> Atmel's AT84AD001B or NS ADC08D1000 ? Preferably without an external
> DMUX-device...
> Using the ADC's internal DEMUX leaves us with 16 500 MHz LVDS lines
> per channel.
>
> Thanks,
>
>   Alex

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

Maxim's MAX108 (8 bits, 1.5Gsps) has internal demux.  It should not be very
difficult to use a Xilinx Virtex-II /Pro device to interface with it.  I
think the FPGA device could run at 500MHz internally.  But it



"Alex" <A_Ungerer@netcourrier.com> wrote in message
news:152c7087.0409060135.30bfa875@posting.google.com...
> Hi,
>
> It's not the first time this question has been asked, but I'd like to
> know todays state of art:
> Are their any devices at Altera, Xilinx or others, capabable of
> handling the fast throughput of high-speed ADCs (1 GS), such as
> Atmel's AT84AD001B or NS ADC08D1000 ? Preferably without an external
> DMUX-device...
> Using the ADC's internal DEMUX leaves us with 16 500 MHz LVDS lines
> per channel.
>
> Thanks,
>
>   Alex
>

Ray Andraka <ray@andraka.com> wrote in message news:<41649515.80D21B73@andraka.com>...
> I did a design a couple years ago in a VirtexE-7 that interfaced to an
> Atmel 1GHz 8 bit ADC.  IIRC, that ADC output 4 samples at a time (perhaps
> there was a matching mux chip).  Once inside the FPGA the signal was
> mixed and FFT'd.  The incoming sample rate was 960MHz.  So yes, the
> answer is most current FPGAs can handle the throughput with some
> clever/careful design.  The new crop of FPGAs are considerably faster
> than the VirtexE devices.

Howdy Ray,

   How fast were your IOB's toggling on that design?  Was it really
960 MHz?  A coworker and I got to looking yesterday, and it appears
that the general purpose IOB hasn't really gained any clock rate
performance since VirtexE - all the way to now with the Virtex4.  We
were hoping to do 1.25 GHz LVDS (or any other standard), but our FAE
is steering us away from doing anything much over 840 or 900 MHz. 
Comments from Xilinx reps also welcome...

BTW, Alex, I agree with Ray.  500 MHz LVDS should be doable without
alot of grief.  Just be aware that the internal termination can be
less than ideal.

Have fun,

   Marc

> Alex wrote:
> >
> > It's not the first time this question has been asked, but I'd like to
> > know todays state of art:
> > Are their any devices at Altera, Xilinx or others, capabable of
> > handling the fast throughput of high-speed ADCs (1 GS), such as
> > Atmel's AT84AD001B or NS ADC08D1000 ? Preferably without an external
> > DMUX-device...
> > Using the ADC's internal DEMUX leaves us with 16 500 MHz LVDS lines
> > per channel.


--
 Marc Randolph
 Reply address is a spam trap.  Please post responses.

Marc,
Care to relate your experiences of the internal termination? I've had no
trouble at 600Mbit/s data and a 600MHz clock. Some of my colleagues have
mentioned that they've run into problems, and they've reverted to fitting
external 100R resistors.
Thanks, Syms.
"Marc Randolph" <mrand@my-deja.com> wrote in message
news:15881dde.0410080333.34287cb4@posting.google.com...
> Just be aware that the internal termination can be
> less than ideal.
>
> Have fun,

240 MHz, 4 samples per clock coming in

Marc Randolph wrote:

> Ray Andraka <ray@andraka.com> wrote in message news:<41649515.80D21B73@andraka.com>...
> > I did a design a couple years ago in a VirtexE-7 that interfaced to an
> > Atmel 1GHz 8 bit ADC.  IIRC, that ADC output 4 samples at a time (perhaps
> > there was a matching mux chip).  Once inside the FPGA the signal was
> > mixed and FFT'd.  The incoming sample rate was 960MHz.  So yes, the
> > answer is most current FPGAs can handle the throughput with some
> > clever/careful design.  The new crop of FPGAs are considerably faster
> > than the VirtexE devices.
>
> Howdy Ray,
>
>    How fast were your IOB's toggling on that design?  Was it really
> 960 MHz?  A coworker and I got to looking yesterday, and it appears
> that the general purpose IOB hasn't really gained any clock rate
> performance since VirtexE - all the way to now with the Virtex4.  We
> were hoping to do 1.25 GHz LVDS (or any other standard), but our FAE
> is steering us away from doing anything much over 840 or 900 MHz.
> Comments from Xilinx reps also welcome...
>
> BTW, Alex, I agree with Ray.  500 MHz LVDS should be doable without
> alot of grief.  Just be aware that the internal termination can be
> less than ideal.
>
> Have fun,
>
>    Marc
>
> > Alex wrote:
> > >
> > > It's not the first time this question has been asked, but I'd like to
> > > know todays state of art:
> > > Are their any devices at Altera, Xilinx or others, capabable of
> > > handling the fast throughput of high-speed ADCs (1 GS), such as
> > > Atmel's AT84AD001B or NS ADC08D1000 ? Preferably without an external
> > > DMUX-device...
> > > Using the ADC's internal DEMUX leaves us with 16 500 MHz LVDS lines
> > > per channel.
>
> --
>  Marc Randolph
>  Reply address is a spam trap.  Please post responses.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

Symon wrote:
 >>Just be aware that the internal termination can be
 >>less than ideal.
 >
> Care to relate your experiences of the internal termination? I've had no
> trouble at 600Mbit/s data and a 600MHz clock. Some of my colleagues have
> mentioned that they've run into problems, and they've reverted to fitting
> external 100R resistors.

Howdy Symon,

    We are using the internal _DT resistors on a V2P7 for receiving a 
LVDS clock that is slightly over 600 MHz, as well as the source 
synchronous data that goes along with it.  It technically works (we 
never have bit errors over all operating conditions), but using a 
differential probe at the vias immediately below the inputs pins show 
that there isn't much margin - the signal quality looks pretty poor.

A more serious problem that we had was with a 600+ MHz GCLK input.  What 
we believe we discovered was that a nearby GCLK input with a single 
ended 3.3V 66 MHz clock was affecting its signal quality enough that 
we'd sometimes miss clocks.  The 66 MHz clock looked good (no excessive 
overshoot or other noise on it).  Lowering the frequency to 311 MHz, 
with no change to routing, fixed the problem.

Have fun,

    Marc

Hi Marc,
I'm getting to the point where I'm gonna give up on the GCLK inputs. I'm
gonna just use ordinary IOBs and use a DCM to fix up the source synchronous
phase. The problem is the positioning of the GCLK balls on the package makes
routing without through vias difficult (I use microvia boards). At 622 MHz,
the inductance of the through vias is starting to hurt the SI.
V. interesting point about the single ended clock. I always source terminate
those, take them in on ordinary IOs, and retime them to a master clock. Too
much pain in the past!
Cheers, Syms.
"Marc Randolph" <mrand@my-deja.com> wrote in message
news:4JOdna9_pM_87ffcRVn-tg@comcast.com...
> Howdy Symon,
>
>     We are using the internal _DT resistors on a V2P7 for receiving a
> LVDS clock that is slightly over 600 MHz, as well as the source
> synchronous data that goes along with it.  It technically works (we
> never have bit errors over all operating conditions), but using a
> differential probe at the vias immediately below the inputs pins show
> that there isn't much margin - the signal quality looks pretty poor.
>
> A more serious problem that we had was with a 600+ MHz GCLK input.  What
> we believe we discovered was that a nearby GCLK input with a single
> ended 3.3V 66 MHz clock was affecting its signal quality enough that
> we'd sometimes miss clocks.  The 66 MHz clock looked good (no excessive
> overshoot or other noise on it).  Lowering the frequency to 311 MHz,
> with no change to routing, fixed the problem.
>
> Have fun,
>
>     Marc

Marc,
My colleague just came clean; he'd fitted an early V2P7 that didn't have the
LVDS_DT functionality. No wonder he had problems that external resistors
fitted.
Cheers, Syms.
"Marc Randolph" <mrand@my-deja.com> wrote in message
news:4JOdna9_pM_87ffcRVn-tg@comcast.com...
> Symon wrote:
>  >>Just be aware that the internal termination can be
>  >>less than ideal.
>  >
> > Care to relate your experiences of the internal termination? I've had no
> > trouble at 600Mbit/s data and a 600MHz clock. Some of my colleagues have
> > mentioned that they've run into problems, and they've reverted to
fitting
> > external 100R resistors.
>
> Howdy Symon,
>
>     We are using the internal _DT resistors on a V2P7 for receiving a
> LVDS clock that is slightly over 600 MHz, as well as the source
> synchronous data that goes along with it.  It technically works (we
> never have bit errors over all operating conditions), but using a
> differential probe at the vias immediately below the inputs pins show
> that there isn't much margin - the signal quality looks pretty poor.
>
> A more serious problem that we had was with a 600+ MHz GCLK input.  What
> we believe we discovered was that a nearby GCLK input with a single
> ended 3.3V 66 MHz clock was affecting its signal quality enough that
> we'd sometimes miss clocks.  The 66 MHz clock looked good (no excessive
> overshoot or other noise on it).  Lowering the frequency to 311 MHz,
> with no change to routing, fixed the problem.
>
> Have fun,
>
>     Marc