I have spent the last 60 days trying to get an answer from Xilinx on their new S3 devices. During a review, it was stated that the new S3s were very sensitive to transients on the I/O pins. Because they made a point to mention this during the review, I posed the following question to Xilinx: "If we look at the incident versus reflected energy and tune the stub (trace) for a worst case match is it possible the driver could be damaged or the chip lock up due to the reflected energy?" "The circuit would be as follows: Spartan III Output ------------------------------ Tunable Stub" I wonder if anyone in this group has asked this question and what was the responce from Xilinx?
Xilinx S3 I/O robustness question
Started by ●September 8, 2003
Reply by ●September 8, 20032003-09-08
When using Spartan-3 FPGAs in an 3.3V LVTTL or LVCMOS application, the output voltage, VCCO, must be within the "narrow" voltage range defined in the EIA/JEDEC JESD8-B specification, namely 3.15V to 3.45V, with a nominal 3.3V value. The primary consideration on Spartan-3 I/Os is to keep the voltage at the pin below the 3.75V absolute maximum specification. Going above 3.75V doesn't immediately destroy the device, but prolonged exposure degrades device lifetime. If the voltage remains below 3.75V, there is no degradation. So, if VCCO should be below 3.45V, how can the voltage at the pin possible reach 3.75V? Mismatched impedance can cause overshoot and undershoot, raising the voltage on the pin by hundreds of millivolts. Properly terminating a trace eliminates or reduces the over/undershoot to acceptable limits. Application note XAPP659 describes some of the techniques to guarantee that signals stay under 3.75V. Although written for the Virtex-II Pro family, these same techniques apply to Spartan-3 FPGAs. Using 3.3V I/O Guidelines in a Virtex-II Pro Design. http://www.xilinx.com/bvdocs/appnotes/xapp659.pdf I hadn't seen this question coming in from our FAE team, so my apologies on not receiving an answer before this time. Should you have any other questions, please feel free to contact me directly. Just be sure to remove the "NOSPAM" from my return E-mail address. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASIC "lecroy" <lecroy7200@chek.com> wrote in message news:9297c711.0309080520.260aa01b@posting.google.com...> I have spent the last 60 days trying to get an answer from Xilinx on > their new S3 devices. During a review, it was stated that the new S3s > were very sensitive to transients on the I/O pins. Because they made a > point to mention this during the review, I posed the following > question to Xilinx: > > "If we look at the incident versus reflected energy and tune the stub > (trace) > for a worst case match is it possible the driver could be damaged or > the > chip lock up due to the reflected energy?" > > "The circuit would be as follows: > Spartan III Output ------------------------------ Tunable Stub" > > I wonder if anyone in this group has asked this question and what was > the responce from Xilinx?
Reply by ●September 9, 20032003-09-09
"Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote in message news:<bjiivv$oae1@cliff.xsj.xilinx.com>...> When using Spartan-3 FPGAs in an 3.3V LVTTL or LVCMOS application, the > output voltage, VCCO, must be within the "narrow" voltage range defined in > the EIA/JEDEC JESD8-B specification, namely 3.15V to 3.45V, with a nominal > 3.3V value. > > The primary consideration on Spartan-3 I/Os is to keep the voltage at the > pin below the 3.75V absolute maximum specification. Going above 3.75V > doesn't immediately destroy the device, but prolonged exposure degrades > device lifetime. If the voltage remains below 3.75V, there is no > degradation. > > So, if VCCO should be below 3.45V, how can the voltage at the pin possible > reach 3.75V? Mismatched impedance can cause overshoot and undershoot, > raising the voltage on the pin by hundreds of millivolts. Properly > terminating a trace eliminates or reduces the over/undershoot to acceptable > limits. Application note XAPP659 describes some of the techniques to > guarantee that signals stay under 3.75V. Although written for the Virtex-II > Pro family, these same techniques apply to Spartan-3 FPGAs. > > Using 3.3V I/O Guidelines in a Virtex-II Pro Design. > http://www.xilinx.com/bvdocs/appnotes/xapp659.pdf >Steve, keep in mind I am talking about the reflected signal on an output only. I was provided the following link from Xilinx. Does this refer to the S3 devices as well, as it conflicts with your original responce? http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=11001 Problem Description: Keywords: FPGA, overshoot, undershoot, reliability Urgency: Standard General Description: Does ringing (overshoot and undershoot) compromise the reliability of an FPGA device? Solution 1: For all FPGA families, ringing signals are not a cause for reliability concerns. To cause such a problem, the Absolution Maximum DC conditions need to be violated for a considerable amount of time (seconds). Keep in mind, however, that ringing can create many functional issues, causing glitches, double- clocking, setup/hold errors, etc.
Reply by ●September 9, 20032003-09-09
--------------A19BB13C19BA9C4BB84FDCD0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit All, A reflection back to an output should not cause a problem, as the nmos is ON, or the pmos is ON, effectively clamping the IOB pin to either gnd or Vcco. If, however, the reflections have enough current to pump up the Vcco, then you have to be careful you do not exceed the max Vcco voltage. It is not recommended to have poor signal integrity (ie unterminated fast edge rate signals) in any design, let alone S3. Austin lecroy wrote:> "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote in message news:<bjiivv$oae1@cliff.xsj.xilinx.com>... > > When using Spartan-3 FPGAs in an 3.3V LVTTL or LVCMOS application, the > > output voltage, VCCO, must be within the "narrow" voltage range defined in > > the EIA/JEDEC JESD8-B specification, namely 3.15V to 3.45V, with a nominal > > 3.3V value. > > > > The primary consideration on Spartan-3 I/Os is to keep the voltage at the > > pin below the 3.75V absolute maximum specification. Going above 3.75V > > doesn't immediately destroy the device, but prolonged exposure degrades > > device lifetime. If the voltage remains below 3.75V, there is no > > degradation. > > > > So, if VCCO should be below 3.45V, how can the voltage at the pin possible > > reach 3.75V? Mismatched impedance can cause overshoot and undershoot, > > raising the voltage on the pin by hundreds of millivolts. Properly > > terminating a trace eliminates or reduces the over/undershoot to acceptable > > limits. Application note XAPP659 describes some of the techniques to > > guarantee that signals stay under 3.75V. Although written for the Virtex-II > > Pro family, these same techniques apply to Spartan-3 FPGAs. > > > > Using 3.3V I/O Guidelines in a Virtex-II Pro Design. > > http://www.xilinx.com/bvdocs/appnotes/xapp659.pdf > > > > Steve, keep in mind I am talking about the reflected signal on an > output only. I was provided the following link from Xilinx. Does > this refer to the S3 devices as well, as it conflicts with your > original responce? > > http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=11001 > > Problem Description: > > Keywords: FPGA, overshoot, undershoot, reliability > > Urgency: Standard > > General Description: > Does ringing (overshoot and undershoot) compromise the reliability of > an FPGA device? > > Solution 1: > > For all FPGA families, ringing signals are not a cause for reliability > concerns. To cause such > a problem, the Absolution Maximum DC conditions need to be violated > for a considerable > amount of time (seconds). > > Keep in mind, however, that ringing can create many functional issues, > causing glitches, double- > clocking, setup/hold errors, etc.--------------A19BB13C19BA9C4BB84FDCD0 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> All, <p>A reflection back to an output should not cause a problem, as the nmos is ON, or the pmos is ON, effectively clamping the IOB pin to either gnd or Vcco. If, however, the reflections have enough current to pump up the Vcco, then you have to be careful you do not exceed the max Vcco voltage. <p>It is not recommended to have poor signal integrity (ie unterminated fast edge rate signals) in any design, let alone S3. <p>Austin <p>lecroy wrote: <blockquote TYPE=CITE>"Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote in message news:<bjiivv$oae1@cliff.xsj.xilinx.com>... <br>> When using Spartan-3 FPGAs in an 3.3V LVTTL or LVCMOS application, the <br>> output voltage, VCCO, must be within the "narrow" voltage range defined in <br>> the EIA/JEDEC JESD8-B specification, namely 3.15V to 3.45V, with a nominal <br>> 3.3V value. <br>> <br>> The primary consideration on Spartan-3 I/Os is to keep the voltage at the <br>> pin below the 3.75V absolute maximum specification. Going above 3.75V <br>> doesn't immediately destroy the device, but prolonged exposure degrades <br>> device lifetime. If the voltage remains below 3.75V, there is no <br>> degradation. <br>> <br>> So, if VCCO should be below 3.45V, how can the voltage at the pin possible <br>> reach 3.75V? Mismatched impedance can cause overshoot and undershoot, <br>> raising the voltage on the pin by hundreds of millivolts. Properly <br>> terminating a trace eliminates or reduces the over/undershoot to acceptable <br>> limits. Application note XAPP659 describes some of the techniques to <br>> guarantee that signals stay under 3.75V. Although written for the Virtex-II <br>> Pro family, these same techniques apply to Spartan-3 FPGAs. <br>> <br>> Using 3.3V I/O Guidelines in a Virtex-II Pro Design. <br>> <a href="http://www.xilinx.com/bvdocs/appnotes/xapp659.pdf">http://www.xilinx.com/bvdocs/appnotes/xapp659.pdf</a> <br>> <p>Steve, keep in mind I am talking about the reflected signal on an <br>output only. I was provided the following link from Xilinx. Does <br>this refer to the S3 devices as well, as it conflicts with your <br>original responce? <p><a href="http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=11001">http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=11001</a> <p> Problem Description: <p>Keywords: FPGA, overshoot, undershoot, reliability <p>Urgency: Standard <p>General Description: <br>Does ringing (overshoot and undershoot) compromise the reliability of <br>an FPGA device? <p>Solution 1: <p>For all FPGA families, ringing signals are not a cause for reliability <br>concerns. To cause such <br>a problem, the Absolution Maximum DC conditions need to be violated <br>for a considerable <br>amount of time (seconds). <p>Keep in mind, however, that ringing can create many functional issues, <br>causing glitches, double- <br>clocking, setup/hold errors, etc.</blockquote> </html> --------------A19BB13C19BA9C4BB84FDCD0--
Reply by ●September 12, 20032003-09-12
Austin, I am guessing that you did not work on the design for the S3. Xilinx has told me everything from there would be no adverse effect from a mismatched output, to causing complete failure. I have kept all of the correspondences if you would like me to post them, but I really don’t see the value in doing so. I am not sure why they seem unable to come up with an answer that they all agree upon. I do not agree with your statement “…, as the nmos is ON, or the pmos is ON, effectively clamping the IOB pin to either gnd or Vcco.” . If we look at an example of an I/O pin (so not a dedicated output), when we transition from a low to high state on the output, the high side driver is sourcing current to the load. As the signal propagates down our transmission line and reaches the end, some energy will reflect back. Let’s use a very high impedance for our termination, so the reflected signal is in phase with the incident. As the reflected signal reaches the output pin it will raise the voltage. Because the driver is sourcing, it has no way to clamp this transient. So, the catch diodes would clamp the reflected signal to a level just over the supply voltage. It’s nice to make the comment about “is not recommended to have poor signal integrity”, but it does not help with the problem. If the devices MTBF decreases with the amount of reflected energy, it would be good to know how close the impedance must be matched. Let’s say you did all of your homework in the layout. You have simulated every trace. Even so, most of the board houses will not guarantee a perfect board is made. There will be a tolerance for the board. Especially if you are playing around with FR-4. So, then we have to ask how close do we need to match the impeadances before we start to see an increase in the failure rates. If this is really an issue with the S3, it will be the first time I have seen this in a digital device. I have seen damage to some higher-powered RF output devices when they have not been matched correctly, due to overheating. Maybe the S3 is so sensitive that it can be damaged this way. Had they not mentioned the S3 being so sensitive during their presentation, I would not have tried to investigate it. Well, Xilinx, can you come up with an answer that you KNOW is correct?
Reply by ●September 12, 20032003-09-12
This is a long and complex e-mail. Let me just correct one fundamental popular misconception below: lecroy wrote:> > Austin, > I do not agree with your statement “…, as the nmos is ON, > or the pmos is ON, effectively clamping the IOB pin to either gnd or > Vcco.” . If we look at an example of an I/O pin (so not a > dedicated output), when we transition from a low to high state on the > output, the high side driver is sourcing current to the load. As the > signal propagates down our transmission line and reaches the end, some > energy will reflect back. Let’s use a very high impedance for > our termination, so the reflected signal is in phase with the > incident. As the reflected signal reaches the output pin it will > raise the voltage. Because the driver is sourcing, it has no way to > clamp this transient. So, the catch diodes would clamp the reflected > signal to a level just over the supply voltage.This is a fairly common misconception. A p-channel output transistor, when active, has a certain impedance, say 10 Ohm. It sources and also sinks current with that impedance . All MOS transistors behave like resistors (at least over a certain voltage range). They conduct current in BOTH directions. Therefore, the active p-channel output transistor will snub the incoming reflection. If you don't believe it, just try it out. It's a simple enough experiment. Peter Alfke, Xilinx Applications
Reply by ●September 12, 20032003-09-12
I just got the following e-mail..... It has some data, but a better article may have been: http://support.xilinx.co.jp/xapp/xapp329.pdf I am still looking for an answer to my question. This is a long and complex e-mail. Let me just correct one fundamental popular misconception below: lecroy wrote:> > Austin, > I do not agree with your statement “…, as the nmos is ON, > or the pmos is ON, effectively clamping the IOB pin to either gnd or > Vcco.” . If we look at an example of an I/O pin (so not a > dedicated output), when we transition from a low to high state on the > output, the high side driver is sourcing current to the load. As the > signal propagates down our transmission line and reaches the end, some > energy will reflect back. Let’s use a very high impedance for > our termination, so the reflected signal is in phase with the > incident. As the reflected signal reaches the output pin it will > raise the voltage. Because the driver is sourcing, it has no way to > clamp this transient. So, the catch diodes would clamp the reflected > signal to a level just over the supply voltage.This is a fairly common misconception. A p-channel output transistor, when active, has a certain impedance, say 10 Ohm. It sources and also sinks current with that impedance . All MOS transistors behave like resistors (at least over a certain voltage range). They conduct current in BOTH directions. Therefore, the active p-channel output transistor will snub the incoming reflection. If you don't believe it, just try it out. It's a simple enough experiment. Peter Alfke, Xilinx Applications
Reply by ●September 12, 20032003-09-12
Let me help you, and rephrase your original question: If a 3.3 V output on Spartan3, going active Low to active High, drives a transmission line of arbitrary length that is open ended at the far end, there will be a return signal that wants to pull the 3S pin higher than Vcco = 3.3 V. Can this cause do damage to the Spartan3 pin? My answer would be: NO. The returning 3.3V wave wants to pull the pin to 6.6 V, but the transmission line impedanec is roughly 50 Ohm, and the chip pull-up impedance is roughly 10 Ohm, so you have a voltage divider that raises the output pin voltage by only 1/6 of the 3.3 V swing = 550 mV. The resulting theoretical 3.85 voltage is really a bit lower since the reflection is not perfect, and there are losses on the line. Also, this spike will only last a few nanoseconds. I would say that this poses no problem. But I have copied Steve Knapp, who handles Spartan applications. He may add his opinion to this. Peter Alfke, Xilinx ============================= lecroy wrote:> I am still looking for an answer to my question. > > �
Reply by ●September 14, 20032003-09-14
>The returning 3.3V wave wants to pull the pin to 6.6 V, but the >transmission line impedanec is roughly 50 Ohm, and the chip pull-up >impedance is roughly 10 Ohm, so you have a voltage divider that raises >the output pin voltage by only 1/6 of the 3.3 V swing = 550 mV. The >resulting theoretical 3.85 voltage is really a bit lower since the >reflection is not perfect, and there are losses on the line. >Also, this spike will only last a few nanoseconds.>I would say that this poses no problem. But I have copied Steve Knapp, >who handles Spartan applications. He may add his opinion to this.There is nothing special about Spartan or FPGAs in this area. Right? Is there a general rule in output pad design that the pad must be rugged enough so that it can't shoot itself in the foot with its own reflections? (I don't remember seeing any warnings about this in data sheets.) What about busses, like PCI, where the driver might be in the middle so the effective line impedance is half of the nominal 50 ohms. (Can it get even lower than that due to capicative loading?) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
Reply by ●September 15, 20032003-09-15
Peter Alfke <peter@xilinx.com> wrote in message news:<3F62569A.BB3294B0@xilinx.com>... What happens at 25 ohms??> My answer would be: NO. > But I have copied Steve Knapp, > who handles Spartan applications. He may add his opinion to this.This is what I have been running into. There seems to be no one at Xilinx who is sure. I had hoped that with this news group being a bit more visable that I could find the right person to ask. Here is David Anderson’s and Paul’s (who both work for Xilinx) responses which are different from yours. In Paul's note, he even talks about asking the factory. ***************************************** So yes the reflected energy can still cause damage, but again if you limit the current to 10mA there shouldn't be any damage. This will be the same limitations as if this was an input. So you can refer to the max specs in the first page of the datasheet. See link below: http://direct.xilinx.com/bvdocs/publications/ds099-3.pdf Mainly you need to take a look at Vin and note 4. When VCCO is 3.0 V or less, VIN overshoot may go as high as VCCO + 1.0 V for up to 11 ns provided that the current entering the I/O pin is limited to 10 mA. Also, when VCCO is 3.0 V or less, VIN undershoot may go as low as -1.0 V for up to 11 ns provided that the current entering the I/O pin is limited to 10 mA. Hope this helps. Regards, David Anderson ***************************************** Going back to your original question, the answer back from the factory is at 3.3 V signaling, it is possible to have reflections damage the part. If you have a particular circuit that you would like to model for you we can do that. In general, IBIS simulation is the way to go in, to insure signal integrity (especially for high speed designs). It should be possible to use the XCITE technology to use a few resistors to impedance match the board layout, assuming that most trace lengths are about the same. Should a few signals be much longer/shorter, XCITE or DCI can be disabled on an IO by IO basis, and these pins can then be terminated separately, if necessary (do IBIS simulation to see if overshoot will be a problem). Hope this helps, Paul ***************************************** I know we have gone back and forth on this, but I think the answer is that there is not an issue. The from what I have seen, the IO on the Spartan III are speced the same as the Virtex II Pro, regarding maximum voltage, and reflections are not an issue with Virtex II Pro. Brain, Please correct me if I am wrong. Again, I believe the initial response was wrong, and that reflections cannot damage the IO. Also, what data can we provide that backs our position. Thanks, Paul
