Xilinx S3 I/O robustness question

hmurray@suespammers.org (Hal Murray) wrote in message news:<vm9n0if1mm4fda@corp.supernews.com>...
> 
> There is nothing special about Spartan or FPGAs in this area.  Right?

Well, let's see if they can answer this. My fear was that they boasted
about their lastest 90nm technology and then turned around and made a
comment about how sensitive it is to transients.
 
> Is there a general rule in output pad design that the pad must
> be rugged enough so that it can't shoot itself in the foot with
> its own reflections?  (I don't remember seeing any warnings about
> this in data sheets.)

 
> What about busses, like PCI, where the driver might be in the middle
> so the effective line impedance is half of the nominal 50 ohms.
> (Can it get even lower than that due to capicative loading?)

I agree, a very interesting question.

lecroy7200@chek.com (lecroy) writes:

> hmurray@suespammers.org (Hal Murray) wrote in message news:<vm9n0if1mm4fda@corp.supernews.com>...

> > What about busses, like PCI, where the driver might be in the middle
> > so the effective line impedance is half of the nominal 50 ohms.
> > (Can it get even lower than that due to capicative loading?)
> 
> I agree, a very interesting question.

PCI requires that the input withstands higher voltages during 11ns, if
I recall correctly.

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se

Hello,

There seems to be a great deal of interest on this topic.

I can tell you what I believe to be the case, and I invite
others from Xilinx to correct what I write here, if I make
any errors.  Most of this I have learned from others.  As
I do not specify or guarantee device behavior, the device
datasheet takes precedence over anything I might say...

In devices like V2Pro and S3, the maximum allowed voltages
(both positive and negative) on the I/O pins form a smaller
window than in some previous families.  In the I/O itself,
there are structures that experience a "stress" that is:

* Pin voltage above GND.
* Pin voltage below VCCO.

When you are using a VCCO of 3.3 volts, you must be diligent
in your board design so that you do not have big reflections
from signal integrity problems.  If you have severe reflections
when using a VCCO of 3.3 volts, you can possibly exceed the
maximum ratings of the device.  Yes, there are diode clamps
on the pin, to both VCCO and GND, but with a VCCO of 3.3v,
the clamps will allow the voltage to rise above the maximum
rating of the device when VCCO is 3.3 volts.

So, when using a VCCO of 3.3v, it is a wise idea to simulate
the I/O you are using, along with your board, to make sure
you are operating the device within the maximum ratings.  I
think this homework is worthwhile, even in other cases.

If IBIS models aren't your thing, and you can't be bothered
with them, you can read XAPP659 for pre-engineered solutions.

> What about busses, like PCI, where the driver might be in
> the middle so the effective line impedance is half of the
> nominal 50 ohms.

This is discussed in detail in XAPP653.  You use a VCCO of
3.0 volts.  It works, is PCI compliant (even if the PCI
bus voltage VIO, which is an independent supply, rises as
high as 3.6 volts -- which is allowed).  Xilinx has verified
this in hardware.  The concept is that lowering VCCO to 3.0v
reduces the "stress" applied:

* (Pin voltage above GND) by clamp diode to VCCO = 3.0v.
* (Pin voltage below VCCO) by reduced VCCO = 3.0v.

An added benefit of our I/O design is that all programmable
I/O are identical, so you won't find yourself forced into a
larger part if (for example) you need more PCI capable I/O.

It is unfortunate that someone (incorrectly) suggested the
device I/O is not "robust".  It is robust, and guaranteed
by Xilinx, when you use it as directed in the FPGA device
datasheet.

Hope that helps,
Eric

>In devices like V2Pro and S3, the maximum allowed voltages
>(both positive and negative) on the I/O pins form a smaller
>window than in some previous families.  ...

Is that window just smaller in terms of volts, or is it
smaller in terms of percent?

Why wasn't this a problem several years ago?  Consider
a 5V IOB or junk CMOS logic.  It would get pulsed to 10 V from
nasty reflections if the clamp diodes didn't do their thing.
Clearly that's way above the max ratings.  So we have been
operating out-of-spec for a long time.

Has technology in this area changed in the past few years?
Have I missed similar discussions in other areas?  (That
would be easy.)

Is there something about the way transistors scale that
I don't know about? (yet)  Are fab lines cutting things
closer now?  ...

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.

Hello Xilinx, are you there???  



lecroy7200@chek.com (lecroy) wrote in message news:<9297c711.0309150524.12171322@posting.google.com>...
> Peter Alfke <peter@xilinx.com> wrote in message news:<3F62569A.BB3294B0@xilinx.com>...
> 
> What happens at 25 ohms??
> 
> 
> > My answer would be: NO.
> > But I have copied Steve Knapp,
> > who handles Spartan applications. He may add his opinion to this.
> 
> This is what I have been running into.  There seems to be no one at
> Xilinx who is sure. I had hoped that with this news group being a bit
> more visable that I could find the right person to ask.  Here is David
> Anderson&#8217;s and Paul&#8217;s (who both work for Xilinx) responses
> which are different from yours.  In Paul's note, he even talks about
> asking the factory.
> 
> 
> 
> *****************************************
> 
> So yes the reflected energy can still cause damage, but again if you
> limit
> the current to 10mA there shouldn't be any damage.  This will be the
> same
> limitations as if this was an input.  So you can refer to the max
> specs
> in the first page of the datasheet.  See link below: 
> http://direct.xilinx.com/bvdocs/publications/ds099-3.pdf
> Mainly you need to take a look at Vin and note 4. When VCCO is 3.0 V
> or
> less, VIN overshoot may go as high as VCCO + 1.0 V for up to 11 ns
> provided
> that the current entering the I/O pin is limited to 10 mA. Also, when
> VCCO
> is 3.0 V or less, VIN undershoot may go as low as -1.0 V for up to 11
> ns
> provided that the current entering the I/O pin is limited to 10 mA.
> 
> Hope this helps.
> 
> Regards,
> David Anderson
> 
> *****************************************
> 
> 
> Going back to your original question, the answer back from the factory
> is at
> 3.3 V signaling, it is possible to have reflections damage the part.
> If you have a particular circuit that you would like to model for you
> we can
> do that.
> 
> In general,  IBIS simulation is the way to go in, to insure signal
> integrity
> (especially for high speed designs).  It should be possible to use the
> XCITE
> technology to use a few resistors to impedance match the board layout,
> assuming that most trace lengths are about the same.  Should a few
> signals be
> much longer/shorter, XCITE or DCI can be disabled on an IO by IO
> basis, and
> these pins can then be terminated separately, if necessary (do IBIS
> simulation to see if overshoot will be a problem).
> 
> Hope this helps,
> Paul
> 
> *****************************************
> 
> 
> I know we have gone back and forth on this, but I think the answer is
> that
> there is not an issue.  The from what I have seen, the IO on the
> Spartan III
> are speced the same as the Virtex II Pro, regarding maximum voltage,
> and
> reflections are not an issue with Virtex II Pro.
> 
> Brain,
> 
> Please correct me if I am wrong.  Again, I believe the initial
> response was
> wrong, and that reflections cannot damage the IO.  Also, what data can
> we
> provide that backs our position.
> 
> Thanks,
> Paul

lecroy,

Of course we are here, and reading.

The confusion is (to many) that the question is what does the reflection back to the driver do to the
driver, right?  This is a fairly obscure distinction, so I would not expect every one of the 200+ hotline
CAEs to get it perfectly right on the first try.

Did you submit multiple cases?  Or call some folks you know?  (IE how did you get multiple answers...) It
would help if you worked this thru the hotline, as they need to learn from their mistakes, and improve
their service sometimes.  If you are talking about it here, then we are not closing the loop!

Well, if the PMOS is ON, then it is really hard for a reflection to drive the output pin to a voltage that
is higher than the specification.  Conversely, if the NMOS is ON, then it is really hard for the reflection
to drive the output pin below ground.

Look at the IBIS simulation at the output pin to see what the voltage excursions are, an be sure they stay
within the specifications sheet and user's guide.

If you have a specific waveform, you may email it to me directly, and I will get the "final word" from the
designers and technology groups.

But let me know the case number, so I can make sure that the hotline is kept in the loop.

Austin

lecroy wrote:

> Hello Xilinx, are you there???
>
> lecroy7200@chek.com (lecroy) wrote in message news:<9297c711.0309150524.12171322@posting.google.com>...
> > Peter Alfke <peter@xilinx.com> wrote in message news:<3F62569A.BB3294B0@xilinx.com>...
> >
> > What happens at 25 ohms??
> >
> >
> > > My answer would be: NO.
> > > But I have copied Steve Knapp,
> > > who handles Spartan applications. He may add his opinion to this.
> >
> > This is what I have been running into.  There seems to be no one at
> > Xilinx who is sure. I had hoped that with this news group being a bit
> > more visable that I could find the right person to ask.  Here is David
> > Anderson&#8217;s and Paul&#8217;s (who both work for Xilinx) responses
> > which are different from yours.  In Paul's note, he even talks about
> > asking the factory.
> >
> >
> >
> > *****************************************
> >
> > So yes the reflected energy can still cause damage, but again if you
> > limit
> > the current to 10mA there shouldn't be any damage.  This will be the
> > same
> > limitations as if this was an input.  So you can refer to the max
> > specs
> > in the first page of the datasheet.  See link below:
> > http://direct.xilinx.com/bvdocs/publications/ds099-3.pdf
> > Mainly you need to take a look at Vin and note 4. When VCCO is 3.0 V
> > or
> > less, VIN overshoot may go as high as VCCO + 1.0 V for up to 11 ns
> > provided
> > that the current entering the I/O pin is limited to 10 mA. Also, when
> > VCCO
> > is 3.0 V or less, VIN undershoot may go as low as -1.0 V for up to 11
> > ns
> > provided that the current entering the I/O pin is limited to 10 mA.
> >
> > Hope this helps.
> >
> > Regards,
> > David Anderson
> >
> > *****************************************
> >
> >
> > Going back to your original question, the answer back from the factory
> > is at
> > 3.3 V signaling, it is possible to have reflections damage the part.
> > If you have a particular circuit that you would like to model for you
> > we can
> > do that.
> >
> > In general,  IBIS simulation is the way to go in, to insure signal
> > integrity
> > (especially for high speed designs).  It should be possible to use the
> > XCITE
> > technology to use a few resistors to impedance match the board layout,
> > assuming that most trace lengths are about the same.  Should a few
> > signals be
> > much longer/shorter, XCITE or DCI can be disabled on an IO by IO
> > basis, and
> > these pins can then be terminated separately, if necessary (do IBIS
> > simulation to see if overshoot will be a problem).
> >
> > Hope this helps,
> > Paul
> >
> > *****************************************
> >
> >
> > I know we have gone back and forth on this, but I think the answer is
> > that
> > there is not an issue.  The from what I have seen, the IO on the
> > Spartan III
> > are speced the same as the Virtex II Pro, regarding maximum voltage,
> > and
> > reflections are not an issue with Virtex II Pro.
> >
> > Brain,
> >
> > Please correct me if I am wrong.  Again, I believe the initial
> > response was
> > wrong, and that reflections cannot damage the IO.  Also, what data can
> > we
> > provide that backs our position.
> >
> > Thanks,
> > Paul

Hi Peter,
      If the pin has 10 Ohms of drive impedance the initial sent pulse
will be less than 3.3V, in fact 3.3V * 50/(10+50) = 2.75V, as the 10
Ohms driver drives a 50 Ohm line. The reflected signal from the
unterminated far end is then 2* 2.75V = 5.5V. This reflected pulse
then increases the voltage at the pin to 3.667, as it's driven from 50
Ohms into a 10 Ohm impedance to VCC = 3.3V. This is less than the
absolute maximum rating of 3.75V. Hooray!
      As you say, this calculation disregards the attenuation due to
the trace propagation function, which will further reduce the
amplitude of the pulse as it travels back and forth down the
transmission line(pcb trace). This is caused by skin effect and stuff.
I guess you could also reduce the drive strength of the pin from the
default 12mA, to increase the source impedance.
       The receiver pin is the one that gets the big hit.
        cheers, Symon.


Peter Alfke <peter@xilinx.com> wrote in message news:<3F62569A.BB3294B0@xilinx.com>...
> Let me help you, and rephrase your original question:
> If a 3.3 V output on Spartan3, going active Low to active High, drives a
> transmission line of arbitrary length that is open ended at the far end,
> there will be a return signal that wants to pull the 3S pin higher than
> Vcco = 3.3 V.
> Can this cause do damage to the Spartan3 pin?
> 
> My answer would be: NO.
> The returning 3.3V wave wants to pull the pin to 6.6 V, but the
> transmission line impedanec is roughly 50 Ohm, and the chip pull-up
> impedance is roughly 10 Ohm, so you have a voltage divider that raises
> the output pin voltage by only 1/6 of the 3.3 V swing = 550 mV. The
> resulting theoretical 3.85 voltage is really a bit lower since the
> reflection is not perfect, and there are losses on the line.
> Also, this spike will only last a few nanoseconds.
> I would say that this poses no problem. But I have copied Steve Knapp,
> who handles Spartan applications. He may add his opinion to this.
> 
> Peter Alfke, Xilinx
> =============================
> lecroy wrote:
> > I am still looking for an answer to my question.
> > 
> > &#4294967295;

Symon,

As if often the case, if you do not run a simulation, you will not get results that are
even close to the truth (by guessing at what is happening).

With a driver impedance of 8.8 ohms (from IBIS simulation), the overshoot/undershoot back
at the driver is less than 100 mV (no pcb or t-line losses, IBIS done with Hyperlynx).

Why does this not scale exactly as you state?  Because the ON resistance of the
transistors is not very linear, and they are less than 8.8 ohms near Vcc or ground.

So, unless you simulate the actual circuit, you will not get the actual result.

Austin

Symon wrote:

> Hi Peter,
>       If the pin has 10 Ohms of drive impedance the initial sent pulse
> will be less than 3.3V, in fact 3.3V * 50/(10+50) = 2.75V, as the 10
> Ohms driver drives a 50 Ohm line. The reflected signal from the
> unterminated far end is then 2* 2.75V = 5.5V. This reflected pulse
> then increases the voltage at the pin to 3.667, as it's driven from 50
> Ohms into a 10 Ohm impedance to VCC = 3.3V. This is less than the
> absolute maximum rating of 3.75V. Hooray!
>       As you say, this calculation disregards the attenuation due to
> the trace propagation function, which will further reduce the
> amplitude of the pulse as it travels back and forth down the
> transmission line(pcb trace). This is caused by skin effect and stuff.
> I guess you could also reduce the drive strength of the pin from the
> default 12mA, to increase the source impedance.
>        The receiver pin is the one that gets the big hit.
>         cheers, Symon.
>
> Peter Alfke <peter@xilinx.com> wrote in message news:<3F62569A.BB3294B0@xilinx.com>...
> > Let me help you, and rephrase your original question:
> > If a 3.3 V output on Spartan3, going active Low to active High, drives a
> > transmission line of arbitrary length that is open ended at the far end,
> > there will be a return signal that wants to pull the 3S pin higher than
> > Vcco = 3.3 V.
> > Can this cause do damage to the Spartan3 pin?
> >
> > My answer would be: NO.
> > The returning 3.3V wave wants to pull the pin to 6.6 V, but the
> > transmission line impedanec is roughly 50 Ohm, and the chip pull-up
> > impedance is roughly 10 Ohm, so you have a voltage divider that raises
> > the output pin voltage by only 1/6 of the 3.3 V swing = 550 mV. The
> > resulting theoretical 3.85 voltage is really a bit lower since the
> > reflection is not perfect, and there are losses on the line.
> > Also, this spike will only last a few nanoseconds.
> > I would say that this poses no problem. But I have copied Steve Knapp,
> > who handles Spartan applications. He may add his opinion to this.
> >
> > Peter Alfke, Xilinx
> > =============================
> > lecroy wrote:
> > > I am still looking for an answer to my question.
> > >
> > > &#4294967295;

Hi Austin,
       Agreed, the simulation is best way! My fag-packet calculation
was a worst case scenario, but still didn't exceed the specification.
Just wanted to confirm to myself there's no problem at the driver end,
and that this talk of using 3V VCCO instead of 3.3V was not needed to
be heeded! (At least for driver pin reasons.)
       I imagine your simulation gets a lower value for the reflection
amplitude because the IBIS model includes rise time information and
chip capacitance, rather than variation of the transistors' impedance.
(But I'm willing to be shot down in flames!!) My calculation assumed
instant (worst case) rise time. How long was your lossless t-line? Was
the flight time longer than the rise time of the signal? (Time for
signal travel is about 180ps/in, typically.)
       So, thanks for doing the simulation, I don't suppose you'd
publish the results just to put this one to bed for good?
            cheers, Syms


Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F6F5B7D.7059DDE5@xilinx.com>...
> Symon,
> 
> As if often the case, if you do not run a simulation, you will not get results that are
> even close to the truth (by guessing at what is happening).
> 
> With a driver impedance of 8.8 ohms (from IBIS simulation), the overshoot/undershoot back
> at the driver is less than 100 mV (no pcb or t-line losses, IBIS done with Hyperlynx).
> 
> Why does this not scale exactly as you state?  Because the ON resistance of the
> transistors is not very linear, and they are less than 8.8 ohms near Vcc or ground.
> 
> So, unless you simulate the actual circuit, you will not get the actual result.
> 
> Austin
> 
> Symon wrote:
> 
> > Hi Peter,
> >       If the pin has 10 Ohms of drive impedance the initial sent pulse
> > will be less than 3.3V, in fact 3.3V * 50/(10+50) = 2.75V, as the 10
> > Ohms driver drives a 50 Ohm line. The reflected signal from the
> > unterminated far end is then 2* 2.75V = 5.5V. This reflected pulse
> > then increases the voltage at the pin to 3.667, as it's driven from 50
> > Ohms into a 10 Ohm impedance to VCC = 3.3V. This is less than the
> > absolute maximum rating of 3.75V. Hooray!
> >       As you say, this calculation disregards the attenuation due to
> > the trace propagation function, which will further reduce the
> > amplitude of the pulse as it travels back and forth down the
> > transmission line(pcb trace). This is caused by skin effect and stuff.
> > I guess you could also reduce the drive strength of the pin from the
> > default 12mA, to increase the source impedance.
> >        The receiver pin is the one that gets the big hit.
> >         cheers, Symon.
> >

>       The receiver pin is the one that gets the big hit.

So how bad is that hit?  How good are the protection diodes?

If the clamp diodes are any good they will reduce the reflection
and make things easier back at the transmitter.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.