Xilinx S3 I/O robustness question

Hi Rick,
     OK, I suppose 'MUST' isn't strictly accurate, you might not care
whether the design works or not! How about 'SHOULD' instead? ;-) Those
signals bouncing back and forth may not affect the circuits functional
operation, but what are you gonna do when it happens on a 5 inch, 32
bit data bus and you can't pass the CE/FCC mark tests? Sell it in
Elbonia, I guess!
     As for ground bounce, if those diodes are dumping energy, be sure
you've decoupled the Rx IC as well as the Tx one! Generally, it's
better not to have to rely on the diodes, don't you think? You end up
trading decoupling capacitors for termination resistors.
     I'm not saying simulate every trace. Simulate one, and layout the
rest accordingly, as I think Austin says in a parallel post. Check the
PCB layout very carefully, watching out for traces that don't comply
with your SI design. I like Austin's idea of adopting a standard
(HSTL, SSTL, PCI), makes it easy.
     cheers, Syms.

rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F71115D.9CC86144@yahoo.com>...
> Symon wrote:
> > 
> > Hi Rick,
> >       As a rule of thumb, when the signal's rise time is faster than
> > 1/6th the time for the signal to get to the other end of the trace,
> > (guess at 170ps/in of track) then you MUST consider the SI
> > implications. (So for a 1ns rise time, i.e. a normal 'FAST' Xilinx
> > pin, you can have 1 inch of track before you have to worry about
> > reflections!) You can find the rise time data in the IBIS files Xilinx
> > provides on their website. Remember, the frequency of the signal isn't
> > important, it's the rise time. Leave those pins in 'SLOW' mode
> > whenever possible!
> 
> But your use of the term "must" is not totally accurate.  The numbers
> you give are a good rule of thumb for when reflections will be
> significant to the signal waveform, but that does not automatically
> indicate a problem will be created.  A data line can bounce around for
> an extra ns or two and won't matter if there is extra time in the
> setup.  Up until now I have not seen a chip rated to exclude ringing or
> overshoot (or undershoot) because of damage.  In fact, most data sheets
> specifically say that this will not be a problem if it only persists for
> a few ns.  
> 
> 
> >       As Austin says, the simulation tools are a BIG help here. Those
> > IC pins drive bloody hard and fast and I would never like to be
> > relying on the clamp diodes to save the day, this dumps energy into
> > the supplies and Austin is not joking when he says that ground bounce
> > is (and will continue to be) a big consideration. There's a reason
> > Xilinx have gone to the trouble of putting DCI on their devices!
> 
> I have not heard of ringing being the cause of ground bounce.  My
> experience has been that ground bounce is caused by the initial current
> slug when an output changes state, not the result of a reflection from
> the other end.  As the numbers that have been posted in this thread have
> indicated, the reflection current is much smaller than the initial
> slug.  
> 
> 
> >       The receivers warrant the most attention as they can appear as
> > an open circuit, the drivers have low impedance and so limit
> > deviations a bit better. It's time to dust off "High-Speed Digital
> > Design" for some bed time reading! There's a new edition out I
> > believe? (Just found it:- High-Speed Signal Propagation: Advanced
> > Black Magic) I also recommend http://www.sigcon.com/ also by Dr.
> > Howard Johnson. More v. helpful stuff there for free!!
> >        HTH, cheers, Syms.
> 
> If I actually have to simulate every signal on the board I am designing,
> it may never get done.  I think there is something wrong with the idea
> that this is a overly complex issue and can't be dealt with in a simpler
> manner.  Or am I missing something of what you are saying?  
> 
> 
> -- 
> 
> Rick "rickman" Collins
>

"Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message
news:3F71B6DF.8885BD55@xilinx.com...

[snip]

> And yes, if you do not pay attention now, you will cause ground bounce
(50 -
> 60 mA of reflection current per IO is possible)

[snip]

Austin,

I appreciate your continued push to get us to look at signal integrity more
closely but please help me out here.  "Ground bounce" that I'm aware of
involves shifting voltage reference thresholds - a voltage effect - due to
the parasitic inductance of the chip's ground to the board's ground plane.
The change in current draw (dI/dt) across the package inductance produces
the voltage change.

Are you suggesting the voltage effect will be caused by the current change
due to reflected energy getting absorbed in the transistors driving those
signals to ground?  This would make some sense to me though I would expect
the current surge to be spread over a much larger time (different
open-circuit lengths) than the original current surges that generated the
synchronous signals getting the reflection.

If my interpretation is not correct and you're suggesting ground-bounce is
related to current rather than current-change related voltage, please help
me understand.

If logic-high reflections are suspected of causing ground bounce, I'd
appreciate some elaboration.  Is there a path for this current through the
ground on-chip?  Are the voltage references not entirely ground-referenced?

Thanks for your help.

John_H,

Take a simple CMOS inverter inside the IC (not part of the IO).  Its switching
threshold is directly related to its ground reference, and its Vcc reference.
Any ground bounce (LdI/dt) or Vcc bounce (same formula) will move ground and
vcc around, even in a perfect bypass world, as there is no "C" used in the
spelling of "LdI/dt."

Basically, assuming perfect bypass caps, a perfect AC short, you still have
that damned LdI/dt to deal with, and the only way to deal with it is to reduce
L, dI, or increase dt, or don't switch everything at once (switch banks on
different phases of the clock).

Now add to the dI/dt that comes from switching outputs, you have a transmission
line with signals launched from chip 1, towards chips 2, and at chip 2, the
overshoot and undershoot of the mismatched signal to the t-line causes the
input clamp diodes to become forward biased.  Now you have a current, and it is
changing, so now there is an additional dI/dt into Vcc, or out of ground at the
RECEIVER.  From the clamp diodes, this current has to traverse the same path as
an output switching current, that is through the various metal layers, and the
package, to get to the ground and Vcc planes in the pcb, so LdI/dt appplies for
these signals (inputs at chip 2) as well, and because of the mismatch,
overshoot and undershoot, you add to the ground bounce/vcc bounce that is from
chip 2's outputs.

All of this shifts the switching threshold of that poor inverter (in chip 1 or
2), and the result is much more jitter than you suspected was in the design.

I have not even taken into account what dI/dt results from the reflected wave
as it comes back to the alread ON driver transistor in chip 1 (the
TRANSMITTER), and then has to go to/from Vcco and ground, which is another
added LdI/dt on top of the previous LdI/dt from the intitial switching of the
output transistor (just will make things worse from not being matched).....

To look at currents in a simulation, place a 1 ohm resistor in series with the
line, and then you can see just what dI/dt's are happening.....(so every
1mV=1mA)

Austin

John_H wrote:

> "Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message
> news:3F71B6DF.8885BD55@xilinx.com...
>
> [snip]
>
> > And yes, if you do not pay attention now, you will cause ground bounce
> (50 -
> > 60 mA of reflection current per IO is possible)
>
> [snip]
>
> Austin,
>
> I appreciate your continued push to get us to look at signal integrity more
> closely but please help me out here.  "Ground bounce" that I'm aware of
> involves shifting voltage reference thresholds - a voltage effect - due to
> the parasitic inductance of the chip's ground to the board's ground plane.
> The change in current draw (dI/dt) across the package inductance produces
> the voltage change.
>
> Are you suggesting the voltage effect will be caused by the current change
> due to reflected energy getting absorbed in the transistors driving those
> signals to ground?  This would make some sense to me though I would expect
> the current surge to be spread over a much larger time (different
> open-circuit lengths) than the original current surges that generated the
> synchronous signals getting the reflection.
>
> If my interpretation is not correct and you're suggesting ground-bounce is
> related to current rather than current-change related voltage, please help
> me understand.
>
> If logic-high reflections are suspected of causing ground bounce, I'd
> appreciate some elaboration.  Is there a path for this current through the
> ground on-chip?  Are the voltage references not entirely ground-referenced?
>
> Thanks for your help.

Symon wrote:
> 
> Hi Rick,
>      OK, I suppose 'MUST' isn't strictly accurate, you might not care
> whether the design works or not! How about 'SHOULD' instead? ;-) Those
> signals bouncing back and forth may not affect the circuits functional
> operation, but what are you gonna do when it happens on a 5 inch, 32
> bit data bus and you can't pass the CE/FCC mark tests? Sell it in
> Elbonia, I guess!

Is there a good market there?  If a 5 inch 32 bit data bus without
termination precludes passing CE/FCC RFI tests, then no PC would ever be
sold.  Few RFI issues are solved purely at the PC board level.  In US
commercial markets, the requirements are very different than consumer
markets as well. 


>      As for ground bounce, if those diodes are dumping energy, be sure
> you've decoupled the Rx IC as well as the Tx one! Generally, it's
> better not to have to rely on the diodes, don't you think? You end up
> trading decoupling capacitors for termination resistors.

That is assuming that the diodes would be triggered.  I seem to recall
that the basic analysis done here showed that this was unlikely.  

>      I'm not saying simulate every trace. Simulate one, and layout the
> rest accordingly, as I think Austin says in a parallel post. Check the
> PCB layout very carefully, watching out for traces that don't comply
> with your SI design. I like Austin's idea of adopting a standard
> (HSTL, SSTL, PCI), makes it easy.

That is the part I am not clear about.  These traces are all individual
circuits.  If you have the luxury of a lot of open board space to route
straight lines here and there, then sure, you can make each one very
similar.  On a small, tight board it will be very difficult to make them
that similar.  If the signal is critical enough to require a simulation,
then I expect I would need to simulate each of them.  

I am surprized that the Spartan 3 chips are so sensitive to over and
undershoot that this has become a major issue.  I have seen lots of high
speed boards and none had FPGAs or any other chips that needed this
degree of analysis to prevent damage.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Austin Lesea wrote:
> 
> Rick,
> 
> Fight it as long as you can, but everyone else is using the more advanced
> tools, and simulating everything (at the companies where they want to be
> successful on the first pcb turn -- as for the others, I don't hear from
> them often anymore....).

Funny.  But I doubt it is very accurate.  I have worked at some of the
larger companies making telecom test equipment and I have yet to meet a
board designer who simulates all of the traces.  The ones I spoke with
only simulate the clock lines or other signal lines when the timing is
tight with no time for settling.  

Like I said, this is the first time I have heard a chip maker claim that
typical ringing and undershoot can cause chip damage.  Of course an
absurdly designed trace and create excessive swings.  But the typical
amount of ringing is normally listed in data sheets as being within spec
for chips.  

> And yes, if you do not pay attention now, you will cause ground bounce (50 -
> 60 mA of reflection current per IO is possible), 

Under what conditions is this "possible"?  I would expect this to be an
extreme case.  The analyis listed here indicated much lower currents
(~35 mA) and only for the brief time (< 1 ns) of the overshoot.  If the
device can't handle these low currents without ground bounce, how can it
possibly provide the much larger currents (> 55 mA) for the initial
level change without ground bounce?  


> and with the Virtex II Pro,
> and Spartan 3 if the IOs are operated at 3.3V, you may exceed the Abs Max
> data sheet limits if you do not pay attention to what you are doing.  And
> that will cause a reduction in the 20 year projected lifetime.  Below 3.0V,
> there are no reliability issues to consider, as the clamp diodes are
> sufficient to protect the IOs.  Smaller, faster, less expensive technology
> from the foundries has some drawbacks:  leakage current, and IO robustness
> at voltages greater than 3.75 volts being two of them.
> 
> The new tools allow for extraction of all pcb parameters, and easy
> simulation of all tracks/traces.  You can also create a design that is
> correct by construction:  use DCI or series or parallel termination, and
> make 50 ohm (or whatever) traces.  Then you do not have to simulate
> everything.

So the DCI in the S3 chips will allow matching of the chip IO impedance
to the trace, right?  

> Or use a standard:  HSTL, SSTL, PCI.  Then you also don't have to think.
> But I also simulate to make sure I haven't missed anything.

I only wish standards really did preclude the "thinking".  I have worked
with RS-232 and many others too long to beleive that.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Rick,

Get off that horse:  'typical' ringing is not the issue here.

Have said it a number of times:  overshoot and undershoot is bad (period), and is
a sign of a bad board design.  The fact that if you have

1) 85C Tj AND
2) you have a power supply at 3.6 volts AND
3) you have crappy SI over long t-lines (which store more energy -- like 12 - 24")

MAY lead to exceeding the Abs Max spec.

The point is that you have to simulate to get good SI, so do so.  While you are at
it, if the SI is terrible, fix it.  If you can't fix it, then make sure you are
within the Abs Max specs.

Austin

rickman wrote:

> Austin Lesea wrote:
> >
> > Rick,
> >
> > Fight it as long as you can, but everyone else is using the more advanced
> > tools, and simulating everything (at the companies where they want to be
> > successful on the first pcb turn -- as for the others, I don't hear from
> > them often anymore....).
>
> Funny.  But I doubt it is very accurate.  I have worked at some of the
> larger companies making telecom test equipment and I have yet to meet a
> board designer who simulates all of the traces.  The ones I spoke with
> only simulate the clock lines or other signal lines when the timing is
> tight with no time for settling.
>
> Like I said, this is the first time I have heard a chip maker claim that
> typical ringing and undershoot can cause chip damage.  Of course an
> absurdly designed trace and create excessive swings.  But the typical
> amount of ringing is normally listed in data sheets as being within spec
> for chips.
>
> > And yes, if you do not pay attention now, you will cause ground bounce (50 -
> > 60 mA of reflection current per IO is possible),
>
> Under what conditions is this "possible"?  I would expect this to be an
> extreme case.  The analyis listed here indicated much lower currents
> (~35 mA) and only for the brief time (< 1 ns) of the overshoot.  If the
> device can't handle these low currents without ground bounce, how can it
> possibly provide the much larger currents (> 55 mA) for the initial
> level change without ground bounce?
>
> > and with the Virtex II Pro,
> > and Spartan 3 if the IOs are operated at 3.3V, you may exceed the Abs Max
> > data sheet limits if you do not pay attention to what you are doing.  And
> > that will cause a reduction in the 20 year projected lifetime.  Below 3.0V,
> > there are no reliability issues to consider, as the clamp diodes are
> > sufficient to protect the IOs.  Smaller, faster, less expensive technology
> > from the foundries has some drawbacks:  leakage current, and IO robustness
> > at voltages greater than 3.75 volts being two of them.
> >
> > The new tools allow for extraction of all pcb parameters, and easy
> > simulation of all tracks/traces.  You can also create a design that is
> > correct by construction:  use DCI or series or parallel termination, and
> > make 50 ohm (or whatever) traces.  Then you do not have to simulate
> > everything.
>
> So the DCI in the S3 chips will allow matching of the chip IO impedance
> to the trace, right?
>
> > Or use a standard:  HSTL, SSTL, PCI.  Then you also don't have to think.
> > But I also simulate to make sure I haven't missed anything.
>
> I only wish standards really did preclude the "thinking".  I have worked
> with RS-232 and many others too long to beleive that.
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX

Last post:

See below,

Austin

rickman wrote:

> Symon wrote:
> >
> > Hi Rick,
> >      OK, I suppose 'MUST' isn't strictly accurate, you might not care
> > whether the design works or not! How about 'SHOULD' instead? ;-) Those
> > signals bouncing back and forth may not affect the circuits functional
> > operation, but what are you gonna do when it happens on a 5 inch, 32
> > bit data bus and you can't pass the CE/FCC mark tests? Sell it in
> > Elbonia, I guess!
>
> Is there a good market there?  If a 5 inch 32 bit data bus without
> termination precludes passing CE/FCC RFI tests, then no PC would ever be
> sold.  Few RFI issues are solved purely at the PC board level.  In US
> commercial markets, the requirements are very different than consumer
> markets as well.

Yes, you can sell garbage.  I don't think that we are talking about that
here:  even game toys have to have just about every government and safety
lab certification known....

>
> >      As for ground bounce, if those diodes are dumping energy, be sure
> > you've decoupled the Rx IC as well as the Tx one! Generally, it's
> > better not to have to rely on the diodes, don't you think? You end up
> > trading decoupling capacitors for termination resistors.
>
> That is assuming that the diodes would be triggered.  I seem to recall
> that the basic analysis done here showed that this was unlikely.

They are triggered at the receive end.  Remember the low drive impedance,
high terminate impedance t-line case tries to as much as double the voltage
at the receive end.  Remember Howard running across the room with his
pointer and banging into the wall (if you have been to one of his great
performances)?  Instructive.

>
>
> >      I'm not saying simulate every trace. Simulate one, and layout the
> > rest accordingly, as I think Austin says in a parallel post. Check the
> > PCB layout very carefully, watching out for traces that don't comply
> > with your SI design. I like Austin's idea of adopting a standard
> > (HSTL, SSTL, PCI), makes it easy.
>
> That is the part I am not clear about.  These traces are all individual
> circuits.  If you have the luxury of a lot of open board space to route
> straight lines here and there, then sure, you can make each one very
> similar.  On a small, tight board it will be very difficult to make them
> that similar.  If the signal is critical enough to require a simulation,
> then I expect I would need to simulate each of them.

Yes.

> I am surprized that the Spartan 3 chips are so sensitive to over and
> undershoot that this has become a major issue.  I have seen lots of high
> speed boards and none had FPGAs or any other chips that needed this
> degree of analysis to prevent damage.

Get off the horse.  It is tired already.  See my other post.  If you are
going to have really bad SI, at 3.6V Vcco, AND 85C Tj, then you may have to
consider the abs max specs.....so do a good SI job, and you will never get
there.

In previous families, there were Abs Max specs, and you could go past them,
too, with poor SI.  This is only different because the numbers are tighter,
and the Vccint is now 1.2 volts, and bad SI will make the design fail to
function a long time before any IO will fail.  Why not encourage designers
to be successful (hey, what a concept!  if the design works, then we sell
more chips!).

I find your tone offensive Austin.  I am simply trying to understand the
issue being discussed by yourself as well as others.  On my board there
will be no traces that are near 12" much less 24" and the power supply
will not be 3.6 volts.  So what you are now talking about is not a
typical board design, but rather a *bad* board design.  That is not what
you said.  Your statements, as well as others, was that *every* board
needs to be simulated.  I agree that clock signals are very sensitive to
signal integrity, but most data lines, that are not excessively long,
will do no hard to most chips and SI issues will only add to the setup
time.  

So if my traces are 6" and under and my Vccio is 3.3 volts or less, is
it likely that a data trace will be at issue if it is not simulated?  As
I said, this is the first time I have heard anyone say that it can be an
issue, *especially* an issue of doing damage to a chip.  

Ringing has been an accepted part of digital logic design since logic
was invented.  It is a problem, not because it exists, but only if it
creats a malfunction.  It can ring for an hour and I won't care if I
have two hours of settling time on my bus.  

If you don't wish to discuss this politely, then please feel free to
ignore my post. 


Austin Lesea wrote:
> 
> Rick,
> 
> Get off that horse:  'typical' ringing is not the issue here.
> 
> Have said it a number of times:  overshoot and undershoot is bad (period), and is
> a sign of a bad board design.  The fact that if you have
> 
> 1) 85C Tj AND
> 2) you have a power supply at 3.6 volts AND
> 3) you have crappy SI over long t-lines (which store more energy -- like 12 - 24")
> 
> MAY lead to exceeding the Abs Max spec.
> 
> The point is that you have to simulate to get good SI, so do so.  While you are at
> it, if the SI is terrible, fix it.  If you can't fix it, then make sure you are
> within the Abs Max specs.
> 
> Austin
> 
> rickman wrote:
> 
> > Austin Lesea wrote:
> > >
> > > Rick,
> > >
> > > Fight it as long as you can, but everyone else is using the more advanced
> > > tools, and simulating everything (at the companies where they want to be
> > > successful on the first pcb turn -- as for the others, I don't hear from
> > > them often anymore....).
> >
> > Funny.  But I doubt it is very accurate.  I have worked at some of the
> > larger companies making telecom test equipment and I have yet to meet a
> > board designer who simulates all of the traces.  The ones I spoke with
> > only simulate the clock lines or other signal lines when the timing is
> > tight with no time for settling.
> >
> > Like I said, this is the first time I have heard a chip maker claim that
> > typical ringing and undershoot can cause chip damage.  Of course an
> > absurdly designed trace and create excessive swings.  But the typical
> > amount of ringing is normally listed in data sheets as being within spec
> > for chips.
> >
> > > And yes, if you do not pay attention now, you will cause ground bounce (50 -
> > > 60 mA of reflection current per IO is possible),
> >
> > Under what conditions is this "possible"?  I would expect this to be an
> > extreme case.  The analyis listed here indicated much lower currents
> > (~35 mA) and only for the brief time (< 1 ns) of the overshoot.  If the
> > device can't handle these low currents without ground bounce, how can it
> > possibly provide the much larger currents (> 55 mA) for the initial
> > level change without ground bounce?
> >
> > > and with the Virtex II Pro,
> > > and Spartan 3 if the IOs are operated at 3.3V, you may exceed the Abs Max
> > > data sheet limits if you do not pay attention to what you are doing.  And
> > > that will cause a reduction in the 20 year projected lifetime.  Below 3.0V,
> > > there are no reliability issues to consider, as the clamp diodes are
> > > sufficient to protect the IOs.  Smaller, faster, less expensive technology
> > > from the foundries has some drawbacks:  leakage current, and IO robustness
> > > at voltages greater than 3.75 volts being two of them.
> > >
> > > The new tools allow for extraction of all pcb parameters, and easy
> > > simulation of all tracks/traces.  You can also create a design that is
> > > correct by construction:  use DCI or series or parallel termination, and
> > > make 50 ohm (or whatever) traces.  Then you do not have to simulate
> > > everything.
> >
> > So the DCI in the S3 chips will allow matching of the chip IO impedance
> > to the trace, right?
> >
> > > Or use a standard:  HSTL, SSTL, PCI.  Then you also don't have to think.
> > > But I also simulate to make sure I haven't missed anything.
> >
> > I only wish standards really did preclude the "thinking".  I have worked
> > with RS-232 and many others too long to beleive that.
> >
> > --
> >
> > Rick "rickman" Collins
> >
> > rick.collins@XYarius.com
> > Ignore the reply address. To email me use the above address with the XY
> > removed.
> >
> > Arius - A Signal Processing Solutions Company
> > Specializing in DSP and FPGA design      URL http://www.arius.com
> > 4 King Ave                               301-682-7772 Voice
> > Frederick, MD 21701-3110                 301-682-7666 FAX

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Austin Lesea wrote:
> 
> Last post:
> 
> See below,
> 
> Austin
> 
> rickman wrote:
> 
> > Symon wrote:
> > >
> > > Hi Rick,
> > >      OK, I suppose 'MUST' isn't strictly accurate, you might not care
> > > whether the design works or not! How about 'SHOULD' instead? ;-) Those
> > > signals bouncing back and forth may not affect the circuits functional
> > > operation, but what are you gonna do when it happens on a 5 inch, 32
> > > bit data bus and you can't pass the CE/FCC mark tests? Sell it in
> > > Elbonia, I guess!
> >
> > Is there a good market there?  If a 5 inch 32 bit data bus without
> > termination precludes passing CE/FCC RFI tests, then no PC would ever be
> > sold.  Few RFI issues are solved purely at the PC board level.  In US
> > commercial markets, the requirements are very different than consumer
> > markets as well.
> 
> Yes, you can sell garbage.  I don't think that we are talking about that
> here:  even game toys have to have just about every government and safety
> lab certification known....

Thank you for that comment Austin.  You are the first person to ever
call my work garbage.  


> > >      As for ground bounce, if those diodes are dumping energy, be sure
> > > you've decoupled the Rx IC as well as the Tx one! Generally, it's
> > > better not to have to rely on the diodes, don't you think? You end up
> > > trading decoupling capacitors for termination resistors.
> >
> > That is assuming that the diodes would be triggered.  I seem to recall
> > that the basic analysis done here showed that this was unlikely.
> 
> They are triggered at the receive end.  Remember the low drive impedance,
> high terminate impedance t-line case tries to as much as double the voltage
> at the receive end.  Remember Howard running across the room with his
> pointer and banging into the wall (if you have been to one of his great
> performances)?  Instructive.
> 
> >
> >
> > >      I'm not saying simulate every trace. Simulate one, and layout the
> > > rest accordingly, as I think Austin says in a parallel post. Check the
> > > PCB layout very carefully, watching out for traces that don't comply
> > > with your SI design. I like Austin's idea of adopting a standard
> > > (HSTL, SSTL, PCI), makes it easy.
> >
> > That is the part I am not clear about.  These traces are all individual
> > circuits.  If you have the luxury of a lot of open board space to route
> > straight lines here and there, then sure, you can make each one very
> > similar.  On a small, tight board it will be very difficult to make them
> > that similar.  If the signal is critical enough to require a simulation,
> > then I expect I would need to simulate each of them.
> 
> Yes.

That is the part that is not practical and I don't believe that it is
required for most signals.  Of course, the sensitivity of the Spartan 3
chips seem to place new boundries on ringing and SI.  According to what
you are saying, signal ringing can do damage to these chips while most
chips in the past have not been that sensitive to it.  


> > I am surprized that the Spartan 3 chips are so sensitive to over and
> > undershoot that this has become a major issue.  I have seen lots of high
> > speed boards and none had FPGAs or any other chips that needed this
> > degree of analysis to prevent damage.
> 
> Get off the horse.  It is tired already.  See my other post.  If you are
> going to have really bad SI, at 3.6V Vcco, AND 85C Tj, then you may have to
> consider the abs max specs.....so do a good SI job, and you will never get
> there.

As I said in my other posts, I have been reading absolute max specs for
years and many have specific exclusions for the brief time of over (or
under) voltage due to ringing.  A couple of ns of overvoltage has never
fried a chip in any lab that I have worked in.  


> In previous families, there were Abs Max specs, and you could go past them,
> too, with poor SI.  This is only different because the numbers are tighter,
> and the Vccint is now 1.2 volts, and bad SI will make the design fail to
> function a long time before any IO will fail.  Why not encourage designers
> to be successful (hey, what a concept!  if the design works, then we sell
> more chips!).

I understand.  But your comments seem to be self contraditory.  First
you tell me the issue is SI which is common to all boards and then you
say the issue is the extreme sensitivity of the new Spartan 3 chips to
SI.  SI is always relative.  In the past the threshold of failure had to
do with delayed settling or double clocking of edge signals.  Now these
new chips are much more sensitive to a new issue, SI induced failure. 
That is all we had to say and admit.  


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Cutting thru the words... I will have to agree with Austin here.. as speeds
go up and voltages go down simulation is going to go from "well maybe" to
"essential"...

Sure your 12 MHz 8031 micro will never need to be simulated.. but your 800
MHz LVDS bus may not even work.. is just a matter of getting relative and
you will find the same with your FPGA... fast edges and fast clocks will
stir a hornets nest .. just be prepared for them..

and you think this is bad .. wait for the Spartan 4 at  .6 instead of .9 ..
give it a bad look and it will jump of the board .. but it will probably run
at a Gig and run on an oily rag

Simon


"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F7388A0.A6A9568A@yahoo.com...
> I find your tone offensive Austin.  I am simply trying to understand the
> issue being discussed by yourself as well as others.  On my board there
> will be no traces that are near 12" much less 24" and the power supply
[snip]