AHB-Slave

Hi,
  When the current AHB slave is busy (hready low) servicing the
Master,but if the master drives IDLE transfer in the next cycle , then
according to the protocol slave should give a zero wait state OKAY
response,but by seeing the hready high for this IDLE response ,master
will drive it's address and data.Later the slave will drive hready for
the pending(previous transfer) service.This is malfuntion the current
transfer...so it is alwayas nessacary to give a zero wait state OKAY
response for an IDLE transfer??

Regards,
M.M.Kumar

mack wrote:

> Hi,
>   When the current AHB slave is busy (hready low) servicing the
> Master,but if the master drives IDLE transfer in the next cycle , then
> according to the protocol slave should give a zero wait state OKAY
> response,but by seeing the hready high for this IDLE response ,master
> will drive it's address and data.Later the slave will drive hready for
> the pending(previous transfer) service.This is malfuntion the current
> transfer...so it is alwayas nessacary to give a zero wait state OKAY
> response for an IDLE transfer??
> 
> Regards,
> M.M.Kumar

Hi there,

A few things you need to know:
- An AHB slave don't have to worry what is on HTRANS when HREADY is low
- An AHB master should not change HTRANS, HADDR, HWRITE, etc when HREADY 
is low (except when it detected error/retry/split responses).

So for the following waveform is perfectly fine:

           T0      T1      T2      T3     T4     T5
         _______ _____________________________ ______
HADDR   ___A___X___B_________________________X______
         _______ _____________________________ ______
HTRANS  ___2___X___IDLE______________________X______
         _______                       _______  _____
HREADY         \_____________________/       \/     \
         _______                        ______ ______
HRDATA/ _______XXXXXXXXXXXXXXXXXXXXXXXX__A___X______X
HWDATA
         _______ _____________________________ ______
HRESP   ___2___X___OKAY______________________X_OKAY_X


In T0, AHB master issue transfer (note that HREADY is high)
In T1, AHB slave start doing the work (putting HREADY to low)
In T2 and T3, despite HTRANS is IDLE in previous cycle, AHB slaves
can ignore it because HREADY is low.
In T4, AHB slave set HREADY to high, so all AHB slave will have to
check what is on HTRANS, HADDR (also HSEL,HWRITE etc).
In T5, AHB slave output a zero wait state OKAY response for the IDLE in T4.

Hope this answered your question.  In addition, question about AHB might 
be better be posted on comp.sys.arm newsgroup. (I know, you might not be 
using ARM stuffs but I guess more people on that newsgroup can answer 
questions on AMBA stuffs).

Regards,
Joe