Vivado parses wicked slow

Vivado is supposed to be really fast, but I've noticed it parses really slowly.  To test this I timed it.  I have a design with about 20 lines of code.  It uses an undeclared reg.  If I try to compile with with Modelsim from the command line, I get an error immediately.  I mean, I can't even time it because the error message appears while my pinky is still on the carriage return.  When I try to synthesize with Vivado, it takes over 20 seconds just to tell me I have an undeclared reg.  That seems like a really long time.

Also, it takes over 3 minutes to P&R this design, which comprises a constant mult with 50 LUTs.  Seems pretty slow.

On Wednesday, July 27, 2016 at 7:21:26 PM UTC-4, Kevin Neilson wrote:
> Vivado is supposed to be really fast, but I've noticed it parses really slowly.  To test this I timed it.  I have a design with about 20 lines of code.  It uses an undeclared reg.  If I try to compile with with Modelsim from the command line, I get an error immediately.  I mean, I can't even time it because the error message appears while my pinky is still on the carriage return.  When I try to synthesize with Vivado, it takes over 20 seconds just to tell me I have an undeclared reg.  That seems like a really long time.
> 
> Also, it takes over 3 minutes to P&R this design, which comprises a constant mult with 50 LUTs.  Seems pretty slow.

If Brand X isn't up to snuff, maybe switch to Brand I, formerly A.

Kevin Jennings

Kevin Neilson wrote:
> Vivado is supposed to be really fast, but I've noticed it parses really slowly.  To test this I timed it.  I have a design with about 20 lines of code..  It uses an undeclared reg.  If I try to compile with with Modelsim from the command line, I get an error immediately.  I mean, I can't even time it because the error message appears while my pinky is still on the carriage return.  When I try to synthesize with Vivado, it takes over 20 seconds just to tell me I have an undeclared reg.  That seems like a really long time.
> 
> Also, it takes over 3 minutes to P&R this design, which comprises a constant mult with 50 LUTs.  Seems pretty slow.

I've just started using Vivado, which was supposed to be a ground-up
totally new software with no inheritance from ISE.  However I have
already noticed that it has some of the same quirks that ISE does.
One thing I noticed in ISE, and it may be related to the time you
take to find an error, is that when you ask to check syntax on one
module it actually parses the entire design hierarchy - even if the
module you wanted checked is only in the project but not a part of
the design hierarchy.  Other quirks include pointing to a different
net when reporting a multi-driven net.  Generally when Vivado reports
a multi-driven net there is one somewhere in the design, just not the
net it is reporting.  Good luck finding the actual net.  I used to
have a similar issue in ISE where it would report GND as multi-driven.

What was clearly a totally new design is the user interface.  Even when
Vivado has the exact same function as ISE you need to know the new name
to find it.  For example, "IP Integrator" is clearly Core Generator
just repackaged for Vivado.

By the way, when you say Vivado took 20 seconds to find the error,
was that running simulation or synthesis?

-- 
Gabor

That is running "synthesis".  It doesn't actually get to synthesis, since there is an elaboration(?) error.  I've actually never used the Vivado simulator.  I could never even get Isim to parse my code, so I haven't tried a Xilinx simulator in years.

On Thursday, July 28, 2016 at 4:47:52 AM UTC+3, KJ wrote:
> On Wednesday, July 27, 2016 at 7:21:26 PM UTC-4, Kevin Neilson wrote:
> > Vivado is supposed to be really fast, but I've noticed it parses really slowly.  To test this I timed it.  I have a design with about 20 lines of code.  It uses an undeclared reg.  If I try to compile with with Modelsim from the command line, I get an error immediately.  I mean, I can't even time it because the error message appears while my pinky is still on the carriage return.  When I try to synthesize with Vivado, it takes over 20 seconds just to tell me I have an undeclared reg.  That seems like a really long time.
> > 
> > Also, it takes over 3 minutes to P&R this design, which comprises a constant mult with 50 LUTs.  Seems pretty slow.
> 
> If Brand X isn't up to snuff, maybe switch to Brand I, formerly A.
> 
> Kevin Jennings

Quartus2 v.15.x suffers from similar problems.
Finding syntax errors in small designs is 10-20 times slower than, for example, in v.9.1.
Not just syntax checks, all phases of processing of small designs in v.15.x feel MUCH slower than in earlier versions. May be, except for timing analysis.

On Friday, July 29, 2016 at 1:32:43 AM UTC+3, already...@yahoo.com wrote:
> On Thursday, July 28, 2016 at 4:47:52 AM UTC+3, KJ wrote:
> > On Wednesday, July 27, 2016 at 7:21:26 PM UTC-4, Kevin Neilson wrote:
> > > Vivado is supposed to be really fast, but I've noticed it parses really slowly.  To test this I timed it.  I have a design with about 20 lines of code.  It uses an undeclared reg.  If I try to compile with with Modelsim from the command line, I get an error immediately.  I mean, I can't even time it because the error message appears while my pinky is still on the carriage return.  When I try to synthesize with Vivado, it takes over 20 seconds just to tell me I have an undeclared reg.  That seems like a really long time.
> > > 
> > > Also, it takes over 3 minutes to P&R this design, which comprises a constant mult with 50 LUTs.  Seems pretty slow.
> > 
> > If Brand X isn't up to snuff, maybe switch to Brand I, formerly A.
> > 
> > Kevin Jennings
> 
> Quartus2 v.15.x suffers from similar problems.
> Finding syntax errors in small designs is 10-20 times slower than, for example, in v.9.1.
> Not just syntax checks, all phases of processing of small designs in v.15.x feel MUCH slower than in earlier versions. May be, except for timing analysis.

Out of interest, I went to quantify my feelings about slowness of small designs in Quartus Prime v.15.1 relatively to previous versions.
Here are results for project with ~250 LEs.

Analysis & Syntesis:
Device       Time Quartus II 9.1 Quartus II 13.1 Quartus Prime 15.1
Cyclone III        2s            2s              N/A
Cyclone IV E       2s            2s              11s
Stratix IV         4s            2s              12s
Cyclone V EB       N/A           2s              12s

Fitter:
Device       Time Quartus II 9.1 Quartus II 13.1 Quartus Prime 15.1
Cyclone III        3s            4s              N/A
Cyclone IV E       2s            4s              4s
Stratix IV         29s           20s             19s
Cyclone V EB       N/A           20s             24s

Timing Analysis:
Device       Time Quartus II 9.1 Quartus II 13.1 Quartus Prime 15.1
Cyclone III        2s            2s              N/A
Cyclone IV E       1s            2s              2s
Stratix IV         4s            3s              3s
Cyclone V EB       N/A           7s              7s


So, slowdown of Analysis & Syntesis is not my imagination, it is very real and certainly pushes the time from category "fast enough" (at least on fast CPU/SSD as in my tests) into category "annoying, disrupts a flow of thinking".

On the other hand, slowdown of fitter is related to new devices (Startix IV and all '5' series) rather than to specific version of Quartus software.

Interesting.  I haven't used Synplify in a while, but I feel like it would parse & synthesize small designs in a matter of seconds.  On the other hand, I made a test case for Vivado:

Vivado 2016.2 Test Case:  Module with One Flipflop
---------------------------------------------------
Synthesis time:  58s
Place & Route:  1:58s
Synth & PAR Together:  2:40

Seems pretty weak.  Does not even include time to "open" design.  I do a lot of small test cases in order to get synthesis right and trying different things on these small designs eats up a lot of my time. 

I might remind you, this design contained one flipflop.  I don't know how fast the computer is, but it was very lightly loaded.

On Tuesday, August 2, 2016 at 7:51:38 PM UTC+3, Kevin Neilson wrote:
> Interesting.  I haven't used Synplify in a while, but I feel like it would parse & synthesize small designs in a matter of seconds.  On the other hand, I made a test case for Vivado:
> 
> Vivado 2016.2 Test Case:  Module with One Flipflop
> ---------------------------------------------------
> Synthesis time:  58s
> Place & Route:  1:58s
> Synth & PAR Together:  2:40
> 
> Seems pretty weak.  Does not even include time to "open" design.  I do a lot of small test cases in order to get synthesis right and trying different things on these small designs eats up a lot of my time. 
> 
> I might remind you, this design contained one flipflop.  I don't know how fast the computer is, but it was very lightly loaded.

I can't confirm your results.
According to my measurement, Vivado handling of small designs *is* awfully slow. but not nearly as slow as you suggest.
I tested with the same design that I used for comparison of versions of Quartus.
The Vivado test computer was somewhat slower than the one I was using with Quartus (Core i7-3770 vs Xeon E3-1271 v3), but also had fast SSD.
I specified the smallest of all Zync devices - xc7z010iclg225-1L.
Synthesis took 23s (wall clock time)
Implementation took 42s 

And remember, my test case was significantly bigger than yours.

So, either something is wrong in your project settings or you should buy faster computer. That is, not more cores, the 2nd CPU core only helps by few per cents and any number of cores above 2 makes no difference at all, but faster cores. And, of course, good fast SSD.

Yes, these results do seem unreasonably bad.  I'll try a different computer.

El jueves, 28 de julio de 2016, 22:53:29 (UTC+10), Gabor escribió:
> Kevin Neilson wrote:
> > Vivado is supposed to be really fast, but I've noticed it parses really slowly.  To test this I timed it.  I have a design with about 20 lines of code..  It uses an undeclared reg.  If I try to compile with with Modelsim from the command line, I get an error immediately.  I mean, I can't even time it because the error message appears while my pinky is still on the carriage return.  When I try to synthesize with Vivado, it takes over 20 seconds just to tell me I have an undeclared reg.  That seems like a really long time.
> > 
> > Also, it takes over 3 minutes to P&R this design, which comprises a constant mult with 50 LUTs.  Seems pretty slow.
> 
> I've just started using Vivado, which was supposed to be a ground-up
> totally new software with no inheritance from ISE.  However I have
> already noticed that it has some of the same quirks that ISE does.
> One thing I noticed in ISE, and it may be related to the time you
> take to find an error, is that when you ask to check syntax on one
> module it actually parses the entire design hierarchy - even if the
> module you wanted checked is only in the project but not a part of
> the design hierarchy.  Other quirks include pointing to a different
> net when reporting a multi-driven net.  Generally when Vivado reports
> a multi-driven net there is one somewhere in the design, just not the
> net it is reporting.  Good luck finding the actual net.  I used to
> have a similar issue in ISE where it would report GND as multi-driven.
> 
> What was clearly a totally new design is the user interface.  Even when
> Vivado has the exact same function as ISE you need to know the new name
> to find it.  For example, "IP Integrator" is clearly Core Generator
> just repackaged for Vivado.
> 
> By the way, when you say Vivado took 20 seconds to find the error,
> was that running simulation or synthesis?
> 
> -- 
> Gabor

The multi-driven net problem was a headache in 
ISE. In vivado you'll also get an obscure report about some net being multi-driven, but you can workaround it quite easily doing a post-synthesis DRC check, it will show more clearly which nets are conflicting.