Hi all, I have over a decade of experience in hardware design, but almost all of it= is in ASIC. I had done some FPGA projects in school, but nothing after tha= t. So after all these years, I want to work on some personal FPGA projects = (mainly to prepare myself for future job interviews). I have the following = two questions. 1. What is an FPGA board that I can buy for this purpose? I am probably loo= king to do something not too basic (since I already have a lot of experienc= e in design), at the same time I do not want to make it a super complicated= full time project either. I prefer Xilinx (but I am open) and something le= ss than $250 will be good. Note that question #2 might also affect the choi= ce of board. 2. Once I have the FPGA board, I would like to implement some design involv= ing network protocol (like TCP/IP, UDP, etc.). However, I have not worked o= n these network layers before and don't have an extensive knowledge on them= either (other than what I had read in school long ago), so I do not have a= very clear picture of what to do. Is there any open source design availabl= e on this? Or any projects with specific definitions that I can understand = and then start implementing? Thanks!
Help me choose an FPGA to design network protocols
Started by ●August 26, 2016
Reply by ●August 27, 20162016-08-27
On 8/26/2016 6:47 PM, PM X wrote:> Hi all, I have over a decade of experience in hardware design, but > almost all of it is in ASIC. I had done some FPGA projects in school, > but nothing after that. So after all these years, I want to work on > some personal FPGA projects (mainly to prepare myself for future job > interviews). I have the following two questions. > > 1. What is an FPGA board that I can buy for this purpose? I am > probably looking to do something not too basic (since I already have > a lot of experience in design), at the same time I do not want to > make it a super complicated full time project either. I prefer Xilinx > (but I am open) and something less than $250 will be good. Note that > question #2 might also affect the choice of board.There are lots of boards available under $100 but likely won't have networking support. Here is one with Ethernet for $200. https://www.arrow.com/en/products/sf2plus-dev-kit/arrow-development-tools#page-8 It uses a Microsemi Smartfusion2 part which contains an ARM CM4 I believe.> 2. Once I have the FPGA board, I would like to implement some design > involving network protocol (like TCP/IP, UDP, etc.). However, I have > not worked on these network layers before and don't have an extensive > knowledge on them either (other than what I had read in school long > ago), so I do not have a very clear picture of what to do. Is there > any open source design available on this? Or any projects with > specific definitions that I can understand and then start > implementing?This is often done with a CPU rather than hardware. TCP/IP protocols are very complicated. As for Open Source, what's wrong with Linux? Or do I misunderstand? -- Rick C
Reply by ●August 27, 20162016-08-27
On Friday, August 26, 2016 at 10:28:45 PM UTC-7, rickman wrote:> On 8/26/2016 6:47 PM, PM X wrote: > > Hi all, I have over a decade of experience in hardware design, but > > almost all of it is in ASIC. I had done some FPGA projects in school, > > but nothing after that. So after all these years, I want to work on > > some personal FPGA projects (mainly to prepare myself for future job > > interviews). I have the following two questions. > > > > 1. What is an FPGA board that I can buy for this purpose? I am > > probably looking to do something not too basic (since I already have > > a lot of experience in design), at the same time I do not want to > > make it a super complicated full time project either. I prefer Xilinx > > (but I am open) and something less than $250 will be good. Note that > > question #2 might also affect the choice of board. > > There are lots of boards available under $100 but likely won't have > networking support. Here is one with Ethernet for $200. > > https://www.arrow.com/en/products/sf2plus-dev-kit/arrow-development-tools#page-8 > > It uses a Microsemi Smartfusion2 part which contains an ARM CM4 I believe. >Sorry, I have some more newbie type questions. How does a board like the above supposed to work considering the ARM core in there? My understanding is that whatever design I implement in HDL runs in the actual FPGA, and any additional software program that I also want to run goes to the ARM processor? So we have two separate runs going on - one in the FPGA and the other in the ARM - and these two can communicate with each other? One other thing I am confused about is that, are the development boards always made by third parties using the FPGA from companies like Xilinx? Or does Xilinx ever make their own development board? I am thinking about getting a board with Xilinx FPGA, probably one of the older Virtex ones. Found this on ebay: http://www.ebay.com/itm/XILINX-VIRTEX-4-XC4VFX100-FPGA-kit-Development-board-XKF4/181791876772 , any comments?> > > 2. Once I have the FPGA board, I would like to implement some design > > involving network protocol (like TCP/IP, UDP, etc.). However, I have > > not worked on these network layers before and don't have an extensive > > knowledge on them either (other than what I had read in school long > > ago), so I do not have a very clear picture of what to do. Is there > > any open source design available on this? Or any projects with > > specific definitions that I can understand and then start > > implementing? > > This is often done with a CPU rather than hardware. TCP/IP protocols > are very complicated. > > As for Open Source, what's wrong with Linux? Or do I misunderstand?I meant some part of the TCP/IP stack implemented in actual hardware and running in the FPGA. For example, a TCP Offload Engine, which implements the whole TCP/IP stack in hardware. Now, I understand that is something enormous and do not want to work on something that big for just a side/hobby project. But something in that area with less complexity is what I am looking for. I just don't have a good idea of what that could be, so having some clear definition will help.
Reply by ●August 28, 20162016-08-28
On 8/27/2016 1:20 PM, PM X wrote:> On Friday, August 26, 2016 at 10:28:45 PM UTC-7, rickman wrote: >> On 8/26/2016 6:47 PM, PM X wrote: >>> Hi all, I have over a decade of experience in hardware design, >>> but almost all of it is in ASIC. I had done some FPGA projects in >>> school, but nothing after that. So after all these years, I want >>> to work on some personal FPGA projects (mainly to prepare myself >>> for future job interviews). I have the following two questions. >>> >>> 1. What is an FPGA board that I can buy for this purpose? I am >>> probably looking to do something not too basic (since I already >>> have a lot of experience in design), at the same time I do not >>> want to make it a super complicated full time project either. I >>> prefer Xilinx (but I am open) and something less than $250 will >>> be good. Note that question #2 might also affect the choice of >>> board. >> >> There are lots of boards available under $100 but likely won't have >> networking support. Here is one with Ethernet for $200. >> >> https://www.arrow.com/en/products/sf2plus-dev-kit/arrow-development-tools#page-8 >> >> >> It uses a Microsemi Smartfusion2 part which contains an ARM CM4 I believe. >> > > Sorry, I have some more newbie type questions. How does a board like > the above supposed to work considering the ARM core in there? My > understanding is that whatever design I implement in HDL runs in the > actual FPGA, and any additional software program that I also want to > run goes to the ARM processor? So we have two separate runs going on > - one in the FPGA and the other in the ARM - and these two can > communicate with each other?Hmmm.... Yes, the ARM will run software written in your favorite sequential language (C, Python, etc) while the FPGA doesn't exactly "run" anything. HDL stands for Hardware Description Language. The HDL doesn't so much get compiled to something that "runs" like a computer program, but rather it is compiled to a configuration file that controls how the various elements of the FPGA hardware are interconnected. The hardware needed in the FPGA is "described". Exactly how the two communicate depends on the vendor. Xilinx and Altera have similar offerings which their own interfaces between the CPU and the FPGA fabric. But basically the CPU program will perform port I/Os or perhaps DMA is used to move data between the FPGA and memory. I haven't done a project with this chip as yet.> One other thing I am confused about is that, are the development > boards always made by third parties using the FPGA from companies > like Xilinx? Or does Xilinx ever make their own development board?The only boards I've seen made by the FPGA vendors tend to be a bit pricier than the ones made by third parties. That's not to say third parties don't make pricey boards, they span a wider range I guess. FPGA vendors make boards so they can sell their chips. Board vendors are selling boards and so make them as fully functional as they can for the price.> I am thinking about getting a board with Xilinx FPGA, probably one of > the older Virtex ones. Found this on ebay: > http://www.ebay.com/itm/XILINX-VIRTEX-4-XC4VFX100-FPGA-kit-Development-board-XKF4/181791876772 > , any comments?Why an older FPGA? Is it price? As you may have figured out, I'm not a big fan of Xilinx. I keep hearing about all manner of issues with their in house tool, Vivaldo. It used to be XST, but the scrapped that. In fact, my very first FPGA design was a Xilinx and during a four month project (or maybe six, I don't recall exactly) I had to ditch tools twice. The first time was to drop the Orcad VHDL tool as it was largely non-functional, switching to the Xilinx tool. Then a second time when Xilinx dropped their earlier tool and only supported a new one. Later they came out with XST and now Vivaldo. I don't get that they have to keep tossing tools. It makes it hard to maintain lifetime support for your product. On the other hand Lattice ditched the chip I have designed on a board I am still making good money from, *very* good money. Fortunately there is sufficient inventory that I won't have to redesign the board for a number of years. At least they use third party synthesis so it isn't a problem to keep supporting products over their lifetime.>>> 2. Once I have the FPGA board, I would like to implement some >>> design involving network protocol (like TCP/IP, UDP, etc.). >>> However, I have not worked on these network layers before and >>> don't have an extensive knowledge on them either (other than what >>> I had read in school long ago), so I do not have a very clear >>> picture of what to do. Is there any open source design available >>> on this? Or any projects with specific definitions that I can >>> understand and then start implementing? >> >> This is often done with a CPU rather than hardware. TCP/IP >> protocols are very complicated. >> >> As for Open Source, what's wrong with Linux? Or do I >> misunderstand? > > I meant some part of the TCP/IP stack implemented in actual hardware > and running in the FPGA. For example, a TCP Offload Engine, which > implements the whole TCP/IP stack in hardware. Now, I understand that > is something enormous and do not want to work on something that big > for just a side/hobby project. But something in that area with less > complexity is what I am looking for. I just don't have a good idea of > what that could be, so having some clear definition will help.I have *no* idea what that could be. As I mentioned, my understanding is the TCP/IP protocol in particular is *very* complex and people don't want to implement their own software on a CPU, much less in hardware. I'm not sure what an "offload engine" would be other than a dedicated CPU, optimized for TCP/IP. But if you have a CM4 in the device, why not use that? To make a hybrid implementation with part of the TCP/IP stack in the CPU and part in the FPGA fabric would require you to intimately understand this algorithm. I believe I've read that a lot of the details are not in any specification, rather are coded in the applications. So you might need to reverse engineer one or more implementations. -- Rick C
Reply by ●August 28, 20162016-08-28
On 27/08/16 18:20, PM X wrote:> I meant some part of the TCP/IP stack implemented in actual hardware and running in the FPGA. For example, a TCP Offload Engine, which implements the whole TCP/IP stack in hardware. Now, I understand that is something enormous and do not want to work on something that big for just a side/hobby project. But something in that area with less complexity is what I am looking for. I just don't have a good idea of what that could be, so having some clear definition will help.Protocol stack offload engines have two fundamental "issues". Firstly the time and latency required to get the packets to/from the main CPU. That significantly affects performance. Secondly the point that TCP is and end-to-end protocol and will correct protocol errors between or in the endpoints. An offload engine becomes the endpoint, so errors between the offload engine and the main CPU will not be corrected. The processing required to reliably transfer packets to/from the main CPU bears a lot of similarity to TCP! TCP in FPGA makes sense where - the lowest latency is required, and - where simplifying assumptions can be made, and - where the end terminal logic is also done in the FPGA e.g. high frequency trading, where they put the business trading rules in hardware to minimise latency
Reply by ●August 28, 20162016-08-28
On Saturday, August 27, 2016 at 11:09:26 PM UTC-7, rickman wrote:> > I am thinking about getting a board with Xilinx FPGA, probably one of > > the older Virtex ones. Found this on ebay: > > http://www.ebay.com/itm/XILINX-VIRTEX-4-XC4VFX100-FPGA-kit-Development-board-XKF4/181791876772 > > , any comments? > > Why an older FPGA? Is it price? >Yes. The newer Virtex boards cost a lot more (the ones using Virtex 6 or 7 run into thousands of dollars). The only reason I am thinking of Xilinx is because it is probably the most used FPGA (along with maybe Altera), so I thought having it on my resume might provide some advantage.> I have *no* idea what that could be. As I mentioned, my understanding > is the TCP/IP protocol in particular is *very* complex and people don't > want to implement their own software on a CPU, much less in hardware. > I'm not sure what an "offload engine" would be other than a dedicated > CPU, optimized for TCP/IP. But if you have a CM4 in the device, why not > use that? >Because the main purpose of this exercise is to design some network protocol in real hardware (FPGA) so I can make myself marketable for jobs in that area. If the network protocol part is too complicated as a side project, then I might just have to write some other (simpler) design and at least become familiar with the FPGA aspects of design.
Reply by ●August 28, 20162016-08-28
On Sunday, August 28, 2016 at 12:11:47 AM UTC-7, Tom Gardner wrote:> On 27/08/16 18:20, PM X wrote: > > I meant some part of the TCP/IP stack implemented in actual hardware and running in the FPGA. For example, a TCP Offload Engine, which implements the whole TCP/IP stack in hardware. Now, I understand that is something enormous and do not want to work on something that big for just a side/hobby project. But something in that area with less complexity is what I am looking for. I just don't have a good idea of what that could be, so having some clear definition will help. > > Protocol stack offload engines have two fundamental "issues". > > Firstly the time and latency required to get the packets > to/from the main CPU. That significantly affects performance. > > Secondly the point that TCP is and end-to-end protocol > and will correct protocol errors between or in the > endpoints. An offload engine becomes the endpoint, so > errors between the offload engine and the main CPU will > not be corrected. > > The processing required to reliably transfer packets > to/from the main CPU bears a lot of similarity to TCP! > > TCP in FPGA makes sense where > - the lowest latency is required, and > - where simplifying assumptions can be made, and > - where the end terminal logic is also done in the FPGA > e.g. high frequency trading, where they put the business > trading rules in hardware to minimise latencyAs a matter of fact, I am doing this to prepare myself for interviews in FPGA design role in high frequency trading (in maybe 3-6 months time). Is there any simpler project that you could suggest that would be in the general area of network protocols (maybe like a stripped down version) that could be implemented in FPGA? Thanks!
Reply by ●August 28, 20162016-08-28
On 28/08/16 19:26, PM X wrote:> On Sunday, August 28, 2016 at 12:11:47 AM UTC-7, Tom Gardner wrote: >> On 27/08/16 18:20, PM X wrote: >>> I meant some part of the TCP/IP stack implemented in actual hardware and running in the FPGA. For example, a TCP Offload Engine, which implements the whole TCP/IP stack in hardware. Now, I understand that is something enormous and do not want to work on something that big for just a side/hobby project. But something in that area with less complexity is what I am looking for. I just don't have a good idea of what that could be, so having some clear definition will help. >> >> Protocol stack offload engines have two fundamental "issues". >> >> Firstly the time and latency required to get the packets >> to/from the main CPU. That significantly affects performance. >> >> Secondly the point that TCP is and end-to-end protocol >> and will correct protocol errors between or in the >> endpoints. An offload engine becomes the endpoint, so >> errors between the offload engine and the main CPU will >> not be corrected. >> >> The processing required to reliably transfer packets >> to/from the main CPU bears a lot of similarity to TCP! >> >> TCP in FPGA makes sense where >> - the lowest latency is required, and >> - where simplifying assumptions can be made, and >> - where the end terminal logic is also done in the FPGA >> e.g. high frequency trading, where they put the business >> trading rules in hardware to minimise latency > > As a matter of fact, I am doing this to prepare myself for interviews in FPGA design role in high frequency trading (in maybe 3-6 months time). Is there any simpler project that you could suggest that would be in the general area of network protocols (maybe like a stripped down version) that could be implemented in FPGA? Thanks!Based on precisely *zero* evidence and only 30s thought, I would guess the networking stack is known technology, whereas business/trading rules are newer. ISTR seeing horrendously expensive boards (worth about 1ms of HFT!) with large numbers of big FPGAs and networking. If that's correct then partitioning the trading rules across FPGAs might be interesting. Or not.
Reply by ●August 28, 20162016-08-28
On 8/28/2016 2:26 PM, PM X wrote:> On Sunday, August 28, 2016 at 12:11:47 AM UTC-7, Tom Gardner wrote: >> On 27/08/16 18:20, PM X wrote: >>> I meant some part of the TCP/IP stack implemented in actual hardware and running in the FPGA. For example, a TCP Offload Engine, which implements the whole TCP/IP stack in hardware. Now, I understand that is something enormous and do not want to work on something that big for just a side/hobby project. But something in that area with less complexity is what I am looking for. I just don't have a good idea of what that could be, so having some clear definition will help. >> >> Protocol stack offload engines have two fundamental "issues". >> >> Firstly the time and latency required to get the packets >> to/from the main CPU. That significantly affects performance. >> >> Secondly the point that TCP is and end-to-end protocol >> and will correct protocol errors between or in the >> endpoints. An offload engine becomes the endpoint, so >> errors between the offload engine and the main CPU will >> not be corrected. >> >> The processing required to reliably transfer packets >> to/from the main CPU bears a lot of similarity to TCP! >> >> TCP in FPGA makes sense where >> - the lowest latency is required, and >> - where simplifying assumptions can be made, and >> - where the end terminal logic is also done in the FPGA >> e.g. high frequency trading, where they put the business >> trading rules in hardware to minimise latency > > As a matter of fact, I am doing this to prepare myself for interviews in FPGA design role in high frequency trading (in maybe 3-6 months time). Is there any simpler project that you could suggest that would be in the general area of network protocols (maybe like a stripped down version) that could be implemented in FPGA? Thanks!Ok, that explains a lot. I would suggest that you start with learning IP stack software. Before you can implement it in the FPGA you have to understand it. So first learn IP stack software. Once you understand how that works you can decide how best to implement it in logic. -- Rick C
Reply by ●August 29, 20162016-08-29
On 8/28/2016 1:51 PM, rickman wrote:> On 8/28/2016 2:26 PM, PM X wrote: >> On Sunday, August 28, 2016 at 12:11:47 AM UTC-7, Tom Gardner wrote: >>> On 27/08/16 18:20, PM X wrote: >>>> I meant some part of the TCP/IP stack implemented in actual hardware >>>> and running in the FPGA. For example, a TCP Offload Engine, which >>>> implements the whole TCP/IP stack in hardware. Now, I understand >>>> that is something enormous and do not want to work on something that >>>> big for just a side/hobby project. But something in that area with >>>> less complexity is what I am looking for. I just don't have a good >>>> idea of what that could be, so having some clear definition will help. >>> >>> Protocol stack offload engines have two fundamental "issues". >>> >>> Firstly the time and latency required to get the packets >>> to/from the main CPU. That significantly affects performance. >>> >>> Secondly the point that TCP is and end-to-end protocol >>> and will correct protocol errors between or in the >>> endpoints. An offload engine becomes the endpoint, so >>> errors between the offload engine and the main CPU will >>> not be corrected. >>> >>> The processing required to reliably transfer packets >>> to/from the main CPU bears a lot of similarity to TCP! >>> >>> TCP in FPGA makes sense where >>> - the lowest latency is required, and >>> - where simplifying assumptions can be made, and >>> - where the end terminal logic is also done in the FPGA >>> e.g. high frequency trading, where they put the business >>> trading rules in hardware to minimise latency >> >> As a matter of fact, I am doing this to prepare myself for interviews >> in FPGA design role in high frequency trading (in maybe 3-6 months >> time). Is there any simpler project that you could suggest that would >> be in the general area of network protocols (maybe like a stripped >> down version) that could be implemented in FPGA? Thanks! > > Ok, that explains a lot. I would suggest that you start with learning > IP stack software. Before you can implement it in the FPGA you have to > understand it. So first learn IP stack software. Once you understand > how that works you can decide how best to implement it in logic.UDP/IP is much simpler the TCP/IP. It is commonly done in FPGAs. For example: http://www.fpga4fun.com/10BASE-T.html OK. It is only 10Base-T. But it's not that different than the 10GbE that we do. You can get a crappy NIC and Basys 3 Artix 7 board for less than $200.00 http://store.digilentinc.com/pmodnic100-network-interface-controller/ It won't be low latency (the NIC has an SPI serial interface) but it will teach concepts. Rob.