I/O switching speed of Xilinx spartan 6 or Altera EP4CE10

Hi,



I am doing a small exercise to learn verilog on FPGAs trying to create a 
FSK31 (ham-radio digital mode) from a FPGA using DDS.


The boards I have use either a Spartan6 (XC6SLX9) or an Cyclon IV (EP4CE10).


The problem to create a digital signal for even the lowest ham-bands 
(137 Khz) using DDS, the I/O pin of the lowest bit needs to switch at 
35.6 Mhz (if using a nice 8bit DDS). For higher bands, the problem is 
even worse, or I need to reduce the resolution of the DDS


My question:
I have looked at the documents by altera or xilinx that describe 
switching-speed of I/O pins of their chips, but -from what I understand 
it all- FPGAs seams to have special I/O driving hardware to drive 
very-high speed interfaces and this does make it all a bit "muddy".


Can somebody explain in (relative) simple and "beginners-lingo" how I/O 
of an FPGA works really works, what kinds of I/O ports there are, and 
how I can know (or change) what is the typical maximum switching-speed 
of an I/O port on a spartan6 or a Cyclone-IV.



Cheerio!
Kristoff

On 1/15/2017 6:43 PM, kristoff wrote:
> Hi,
>
>
>
> I am doing a small exercise to learn verilog on FPGAs trying to create a
> FSK31 (ham-radio digital mode) from a FPGA using DDS.

First of all, do you mean PSK31 or FSK31?  I see both are used, but 
PSK31 is much more common.

Are you looking to generate an audio signal that you can feed into the 
mic input of a transmitter?  Or are you looking to produce the RF signal 
directly?


> The boards I have use either a Spartan6 (XC6SLX9) or an Cyclon IV
> (EP4CE10).
>
>
> The problem to create a digital signal for even the lowest ham-bands
> (137 Khz) using DDS, the I/O pin of the lowest bit needs to switch at
> 35.6 Mhz (if using a nice 8bit DDS). For higher bands, the problem is
> even worse, or I need to reduce the resolution of the DDS

I have no idea what you mean by this.  A DDS typically creates sine 
waves although there are times a square wave is appropriate.  Or is this 
an all digital process?  Are you talking about the digital output which 
will drive a DAC?


> My question:
> I have looked at the documents by altera or xilinx that describe
> switching-speed of I/O pins of their chips, but -from what I understand
> it all- FPGAs seams to have special I/O driving hardware to drive
> very-high speed interfaces and this does make it all a bit "muddy".

What part is muddy?


> Can somebody explain in (relative) simple and "beginners-lingo" how I/O
> of an FPGA works really works, what kinds of I/O ports there are, and
> how I can know (or change) what is the typical maximum switching-speed
> of an I/O port on a spartan6 or a Cyclone-IV.

Better would be if you can explain what you intend to do with the output 
from the FPGA?  Is this a digital output or an analog output?

-- 

Rick C

kristoff wrote:


> I have looked at the documents by altera or xilinx that describe
> switching-speed of I/O pins of their chips, but -from what I understand
> it all- FPGAs seams to have special I/O driving hardware to drive
> very-high speed interfaces and this does make it all a bit "muddy".
> 
In general, you would have the I/O pad driven by a FF clocked at some system 
frequency.  So, you could only change to output state at one of those clock 
edges.  At least on Xilinx, it is possible to run an output directly from 
some signal from the FPGA fabric.  This is generally frowned upon as the 
delay between internal and I/O can be less well defined.

Xilinx does have SERDES components that can run much faster than the rest of 
the chip, and some of them can get up to the GHz clock range.  These can 
serialize a number of parallel bits running at some lower rate into a serial 
stream at much higher rates.  These FPGAs have a limited number of these 
SERDES components.  You instantiate them using a tool provided by Xilinx.
> 
> Can somebody explain in (relative) simple and "beginners-lingo" how I/O
> of an FPGA works really works, what kinds of I/O ports there are, and
> how I can know (or change) what is the typical maximum switching-speed
> of an I/O port on a spartan6 or a Cyclone-IV.
I only know Xilinx.  Each I/O pad has a receiver and a transmitter that can 
be set up as tri-state.  There are also FFs that can be selected into the 
input and output paths.  You can define in the HDL how you want the I/O pad 
to operate.  Also, the Xilinx parts have controllable delays that be used to 
adjust for timing issues between external parts and the FPGA.  The outputs 
are VERY fast, you can probably run a 300 MHz clock on the output FFs and 
thus get 150 MHz square waves out.  

You also have selectable voltage standards on these I/Os, generally selected 
in banks and powered by different voltages.  So, you can have an FPGA with 
3.3 V signals on one side, and 1.8 V signals on the other.  This is all set 
up in the tools, with a constraint file that defines the I/O standard for 
each pin.

Jon

Jon Elson wrote:
> 
> Xilinx does have SERDES components that can run much faster than the rest of 
> the chip, and some of them can get up to the GHz clock range.  These can 
> serialize a number of parallel bits running at some lower rate into a serial 
> stream at much higher rates.

The maximum switching rate on a pin is very dependent on the IO standard
selected.  To get the GHz rates you need to use a differential output
standard like LVDS.  Single-ended like LVCMOS defaults to using a
slew-rate limited driver, which will further reduce the effective
switching speed.  Make sure you set the slew rate to FAST on the
high-speed pin if it is running single-ended.

For Spartan-6 you also need to be aware that the device is not
homogenous.  Typically these parts have "top and bottom" banks
of I/O and "left and right" banks of I/O.  Some banks have more
drive capability on single-ended standards, but don't have the
capability to do differential output.  Check your board to make
sure that the I/O bank type you need is actually brought out
to a connector.

Xilinx documentation is somewhat fragmented.  You don't get it
all in one "datasheet" like you would on simpler devices.  They
have a data sheet with electrical characteristics, and a lot of
"user guides" describing functionality like I/O, configuration,
and clocking.  As far as I can remember, they generally don't
publish maximum switching rate numbers on all I/O types.  You'd
need to run IBIS simulations to get most of them.  LVDS maximum
bit rates may be specified in the family overview document,
because they will be the highest rates possible using general
I/O.  If you have a Spartan-6 LXT device (with gigabit transceivers)
you also have the option to use those to achieve much higher
switching rates, but the interface insn't so simple.

If you decide to use the Xilinx board rather than Altera, you can
get a lot more insight going on the Xilinx forums, where even the
Xilinx employees are available to answer questions.

Good luck on your project, it sounds interesting.

-- 
Gabor

On Sun, 15 Jan 2017 22:17:53 -0500, rickman wrote:

> On 1/15/2017 6:43 PM, kristoff wrote:
>> Hi,
>>
>>
>>
>> I am doing a small exercise to learn verilog on FPGAs trying to create
>> a FSK31 (ham-radio digital mode) from a FPGA using DDS.
> 
> First of all, do you mean PSK31 or FSK31?  I see both are used, but
> PSK31 is much more common.
> 
> Are you looking to generate an audio signal that you can feed into the
> mic input of a transmitter?  Or are you looking to produce the RF signal
> directly?
> 
> 
>> The boards I have use either a Spartan6 (XC6SLX9) or an Cyclon IV
>> (EP4CE10).
>>
>>
>> The problem to create a digital signal for even the lowest ham-bands
>> (137 Khz) using DDS, the I/O pin of the lowest bit needs to switch at
>> 35.6 Mhz (if using a nice 8bit DDS). For higher bands, the problem is
>> even worse, or I need to reduce the resolution of the DDS
> 
> I have no idea what you mean by this.  A DDS typically creates sine
> waves although there are times a square wave is appropriate.  Or is this
> an all digital process?  Are you talking about the digital output which
> will drive a DAC?
> 
> 
>> My question:
>> I have looked at the documents by altera or xilinx that describe
>> switching-speed of I/O pins of their chips, but -from what I understand
>> it all- FPGAs seams to have special I/O driving hardware to drive
>> very-high speed interfaces and this does make it all a bit "muddy".
> 
> What part is muddy?
> 
> 
>> Can somebody explain in (relative) simple and "beginners-lingo" how I/O
>> of an FPGA works really works, what kinds of I/O ports there are, and
>> how I can know (or change) what is the typical maximum switching-speed
>> of an I/O port on a spartan6 or a Cyclone-IV.
> 
> Better would be if you can explain what you intend to do with the output
> from the FPGA?  Is this a digital output or an analog output?

If he's doing what I think he's doing he wants to produce RF directly 
from a DAC that is connected to the FPGA.

-- 
Tim Wescott
Control systems, embedded software and circuit design
I'm looking for work!  See my website if you're interested
http://www.wescottdesign.com

On Mon, 16 Jan 2017 00:43:25 +0100, kristoff wrote:

> Hi,
> 
> 
> 
> I am doing a small exercise to learn verilog on FPGAs trying to create a
> FSK31 (ham-radio digital mode) from a FPGA using DDS.
> 
> 
> The boards I have use either a Spartan6 (XC6SLX9) or an Cyclon IV
> (EP4CE10).
> 
> 
> The problem to create a digital signal for even the lowest ham-bands
> (137 Khz) using DDS, the I/O pin of the lowest bit needs to switch at
> 35.6 Mhz (if using a nice 8bit DDS). For higher bands, the problem is
> even worse, or I need to reduce the resolution of the DDS

How are you arriving at that number?  In a world where perfect 
reconstruction filters exist, you can run the output frequency all the 
way up to half of the clock frequency.  If you want to make the 
reconstruction filtering much easier you'd limit the output to something 
like Fs/4 -- and 548kHz is a hell of a lot less than 35.6MHz.

This article should help to clarify your thinking:
http://wescottdesign.com/articles/Sampling/sampling.pdf

As for your question about I/O rates: probably up to hundreds of MHz, but 
it somewhat depends on your abilities.  If you don't want to spread your 
output spectrum from the DDS you may want to make a stable clock source 
external of the FPGA and use that both to drive the DAC's sample clock 
and the FPGA.  At least the last time I checked (which, granted, was 20 
years ago), internal FPGA circuitry was too noisy to use as sampling 
clocks in communications applications.

-- 
Tim Wescott
Control systems, embedded software and circuit design
I'm looking for work!  See my website if you're interested
http://www.wescottdesign.com

Tim Wescott <tim@seemywebsite.com> wrote:
> If he's doing what I think he's doing he wants to produce RF directly 
> from a DAC that is connected to the FPGA.

I think the first step here is to select the right DAC, that is able to be
be driven from the FPGA and has the necessary properties on the analogue
end.

For instance, a randomly selected example might be:
https://www.maximintegrated.com/en/products/analog/data-converters/digital-to-analog-converters/MAX5891.html
which looks to have generous output bandwidth.

That takes 16 bits of LVDS plus an LVDS clock. An FPGA should be able to
generate that.

However the next question is: can your selected FPGA manage it, or do you
need a more fancy FPGA?  That's basically a case of pin-counting and looking
at the specs for LVDS drivers.  Though it's worth doing a dummy run before
you commit (before designing your board, write some code to generate
maximum-frequency square wave samples and drive them out the correct pins),
because the tool will tell you if you overlooked something or misunderstood.

Or, if you already have an eval board, what DAC do you have?

Theo

Hi Tim,



I am sorry but I am a bit short on time today. (to much fun things to 
do, to little time), so I will just reply to your message.

However, I do also like to thank everybody who replied (you, Gabor, Jon, 
Rickman). I'll try to answers to all the remarks at once.




First, an answer to your other message, and to explain my setup.

Yes, indeed, the goal is to create the RF-signal directly from the FPGA.

As said, this is at this point just an exercise, by trying to make 
something that is more-or-less "usefull" and -at the same time- a way 
for me to learn more about FPGAs. At the same time, it's also my first 
project in verilog.


So, I know, you can do a lot by adding analog circuits after the DAC, 
but I am at this point trying to learn what exactly a FPGA is capable of 
doing.

It started after a fellow-ham in our radio-club have a talk on "digital 
modes" a couple of weeks ago, mentioning PSK31.
(yes, "rickman", you are correct, it is PSK31, not FSK. My error).

As the talk also mentioned building your own beacon for CW, QRSS (very 
slow CW) or WSPR, mainly based on AD9850, I thought "it should be 
possible to do this for PSK31 too.

The problem is that PSK31 is not just phase-shift keying. To reduce 
splatter, it reduces the amplitute of the signal to zero just before 
change is phase-shift is done. (in fact, the signal is multiplied with a 
cosine signal)
(see here: 
https://upload.wikimedia.org/wikipedia/commons/7/78/Bpsk31bits.png)
So it was not possible to use a AD9850 for that and -I think- a FPGA 
would be ideal for this.


My idea was to port the design of (I think) a 2011 "elektor" project for 
a DDS from using a microcontroller (ATtiny) to using a FPGA. The design 
is very basic, using a R/2R ladder as DAC.

The DDS is based on a 256-value sinewave table with 8 bits of 
resolution. This drives 8 output-ports connected to the R/2R ladder.

So, for the best "quality" (stepping 1 value per clock-cycle in a 256 
value table) the frequency of the resulting sinewave is fclock/256.
Or, going the other way, for a 137 Khz sinewave, you need a 35.072 Mhz 
clock. (which should of course not be a problem for a FPGA).


But, as said, this does mean that if you have a 8 bit R/2R ladder, you 
risk have the port of the lowest bit switch at 35.072 Mhz (hum ... come 
to think of it, probably only half of that).


And this got me thinking about how fast you can actually switch a I/O 
pin of a FPGA. I know that FPGAs are used for "very high speed" devices, 
.. so I guess that the pins are able to switch very fast, ... but how fast.
And, ... how do you actually interface it?


I noticed that the pinplanner in the Altera software allows you to 
select a number of different modes for I/O pins: different voltages, 
HSTL class I and II, LVCMOS, LVTTL, LVDS/PPDS/RSDS (in different 
variants), SSTL.

So I started reading documentation about all these different modes, what 
speed they offer, how to interface them, etc. but the information was 
-at least to me- quite daunting.

(hence my question).


BTW. My apologies to everybody for not making my original question more 
clear. But then, the result was that I got some information that was not 
planned, but not less interesting never-the-less :-)



On 16-01-17 18:20, Tim Wescott wrote:
>> The problem to create a digital signal for even the lowest ham-bands
>> (137 Khz) using DDS, the I/O pin of the lowest bit needs to switch at
>> 35.6 Mhz (if using a nice 8bit DDS). For higher bands, the problem is
>> even worse, or I need to reduce the resolution of the DDS
>
> How are you arriving at that number?  In a world where perfect
> reconstruction filters exist, you can run the output frequency all the
> way up to half of the clock frequency.  If you want to make the
> reconstruction filtering much easier you'd limit the output to something
> like Fs/4 -- and 548kHz is a hell of a lot less than 35.6MHz.
>
> This article should help to clarify your thinking:
> http://wescottdesign.com/articles/Sampling/sampling.pdf

Thanks for the link. (actually quite an interesting read) :-)



> As for your question about I/O rates: probably up to hundreds of MHz, but
> it somewhat depends on your abilities.  If you don't want to spread your
> output spectrum from the DDS you may want to make a stable clock source
> external of the FPGA and use that both to drive the DAC's sample clock
> and the FPGA.  At least the last time I checked (which, granted, was 20
> years ago), internal FPGA circuitry was too noisy to use as sampling
> clocks in communications applications.

That is interesting information. Thanks. :-)


Again thanks to you and to all who replied.

As said, currently this is just an exercise for myself, but the goal 
does is to actually build this thing: get the analog backend of the this 
done correctly and use it -as a portable FSK31-enabled beacon-, perhaps 
for SOTA-operations.



Cheerio! Kr. Bonne.

On Tue, 17 Jan 2017 00:59:11 +0100, kristoff wrote:

> Hi Tim,
> 
> 
> 
> I am sorry but I am a bit short on time today. (to much fun things to
> do, to little time), so I will just reply to your message.
> 
> However, I do also like to thank everybody who replied (you, Gabor, Jon,
> Rickman). I'll try to answers to all the remarks at once.
> 
> 
> 
> 
> First, an answer to your other message, and to explain my setup.
> 
> Yes, indeed, the goal is to create the RF-signal directly from the FPGA.
> 
> As said, this is at this point just an exercise, by trying to make
> something that is more-or-less "usefull" and -at the same time- a way
> for me to learn more about FPGAs. At the same time, it's also my first
> project in verilog.
> 
> 
> So, I know, you can do a lot by adding analog circuits after the DAC,
> but I am at this point trying to learn what exactly a FPGA is capable of
> doing.
> 
> It started after a fellow-ham in our radio-club have a talk on "digital
> modes" a couple of weeks ago, mentioning PSK31.
> (yes, "rickman", you are correct, it is PSK31, not FSK. My error).
> 
> As the talk also mentioned building your own beacon for CW, QRSS (very
> slow CW) or WSPR, mainly based on AD9850, I thought "it should be
> possible to do this for PSK31 too.
> 
> The problem is that PSK31 is not just phase-shift keying. To reduce
> splatter, it reduces the amplitute of the signal to zero just before
> change is phase-shift is done. (in fact, the signal is multiplied with a
> cosine signal)
> (see here:
> https://upload.wikimedia.org/wikipedia/commons/7/78/Bpsk31bits.png)
> So it was not possible to use a AD9850 for that and -I think- a FPGA
> would be ideal for this.
> 
> 
> My idea was to port the design of (I think) a 2011 "elektor" project for
> a DDS from using a microcontroller (ATtiny) to using a FPGA. The design
> is very basic, using a R/2R ladder as DAC.
> 
> The DDS is based on a 256-value sinewave table with 8 bits of
> resolution. This drives 8 output-ports connected to the R/2R ladder.
> 
> So, for the best "quality" (stepping 1 value per clock-cycle in a 256
> value table) the frequency of the resulting sinewave is fclock/256.
> Or, going the other way, for a 137 Khz sinewave, you need a 35.072 Mhz
> clock. (which should of course not be a problem for a FPGA).

The best quality by what measure?  You're really not going to improve 
things much by clocking that fast.  And what if you get your hands on a 
16-bit DAC?  Will you be asking how to do this at several GHz?

> But, as said, this does mean that if you have a 8 bit R/2R ladder, you
> risk have the port of the lowest bit switch at 35.072 Mhz (hum ... come
> to think of it, probably only half of that).

Rolling your own DAC from resistors and the output pins of a ginormous 
digital device is not a recipe for high quality.  Unless you really, 
really know what you're doing here you're giving up a lot more than 
you're going to get by over-clocking your DDS so severely.

> And this got me thinking about how fast you can actually switch a I/O
> pin of a FPGA. I know that FPGAs are used for "very high speed" devices,
> .. so I guess that the pins are able to switch very fast, ... but how
> fast.
> And, ... how do you actually interface it?
> 
> 
> I noticed that the pinplanner in the Altera software allows you to
> select a number of different modes for I/O pins: different voltages,
> HSTL class I and II, LVCMOS, LVTTL, LVDS/PPDS/RSDS (in different
> variants), SSTL.
> 
> So I started reading documentation about all these different modes, what
> speed they offer, how to interface them, etc. but the information was
> -at least to me- quite daunting.
> 
> (hence my question).

My suggestion:  If you stick to LVCMOS, then you won't be able to run 
super-blazing-fast, but you'll be plenty fast to clock a DAC at 50 or 
100MHz.  That should be plenty, and will, in fact, probably be 
challenging your PCB layout abilities (it gets ever-less trivial as the 
frequencies go up, although keeping the parts close together should help).

You will be far happier if you just buy a DAC.  Get something that's good 
for a sampling rate of around 50MHz, but that has an internal latch.  I 
suspect that there will be affordable 12-bit ones, even.

And then, since you need to put a good bandlimit filter in there _anyway_ 
to conform to good RF practice -- call it a "reconstruction filter" and 
be happy.

-- 
Tim Wescott
Control systems, embedded software and circuit design
I'm looking for work!  See my website if you're interested
http://www.wescottdesign.com

On 1/16/2017 6:59 PM, kristoff wrote:
> Hi Tim,
>
>
>
> I am sorry but I am a bit short on time today. (to much fun things to
> do, to little time), so I will just reply to your message.
>
> However, I do also like to thank everybody who replied (you, Gabor, Jon,
> Rickman). I'll try to answers to all the remarks at once.
>
>
>
>
> First, an answer to your other message, and to explain my setup.
>
> Yes, indeed, the goal is to create the RF-signal directly from the FPGA.
>
> As said, this is at this point just an exercise, by trying to make
> something that is more-or-less "usefull" and -at the same time- a way
> for me to learn more about FPGAs. At the same time, it's also my first
> project in verilog.
>
>
> So, I know, you can do a lot by adding analog circuits after the DAC,
> but I am at this point trying to learn what exactly a FPGA is capable of
> doing.
>
> It started after a fellow-ham in our radio-club have a talk on "digital
> modes" a couple of weeks ago, mentioning PSK31.
> (yes, "rickman", you are correct, it is PSK31, not FSK. My error).
>
> As the talk also mentioned building your own beacon for CW, QRSS (very
> slow CW) or WSPR, mainly based on AD9850, I thought "it should be
> possible to do this for PSK31 too.
>
> The problem is that PSK31 is not just phase-shift keying. To reduce
> splatter, it reduces the amplitute of the signal to zero just before
> change is phase-shift is done. (in fact, the signal is multiplied with a
> cosine signal)
> (see here:
> https://upload.wikimedia.org/wikipedia/commons/7/78/Bpsk31bits.png)
> So it was not possible to use a AD9850 for that and -I think- a FPGA
> would be ideal for this.
>
>
> My idea was to port the design of (I think) a 2011 "elektor" project for
> a DDS from using a microcontroller (ATtiny) to using a FPGA. The design
> is very basic, using a R/2R ladder as DAC.
>
> The DDS is based on a 256-value sinewave table with 8 bits of
> resolution. This drives 8 output-ports connected to the R/2R ladder.
>
> So, for the best "quality" (stepping 1 value per clock-cycle in a 256
> value table) the frequency of the resulting sinewave is fclock/256.
> Or, going the other way, for a 137 Khz sinewave, you need a 35.072 Mhz
> clock. (which should of course not be a problem for a FPGA).
>
>
> But, as said, this does mean that if you have a 8 bit R/2R ladder, you
> risk have the port of the lowest bit switch at 35.072 Mhz (hum ... come
> to think of it, probably only half of that).
>
>
> And this got me thinking about how fast you can actually switch a I/O
> pin of a FPGA. I know that FPGAs are used for "very high speed" devices,
> .. so I guess that the pins are able to switch very fast, ... but how fast.
> And, ... how do you actually interface it?
>
>
> I noticed that the pinplanner in the Altera software allows you to
> select a number of different modes for I/O pins: different voltages,
> HSTL class I and II, LVCMOS, LVTTL, LVDS/PPDS/RSDS (in different
> variants), SSTL.
>
> So I started reading documentation about all these different modes, what
> speed they offer, how to interface them, etc. but the information was
> -at least to me- quite daunting.
>
> (hence my question).
>
>
> BTW. My apologies to everybody for not making my original question more
> clear. But then, the result was that I got some information that was not
> planned, but not less interesting never-the-less :-)
>
>
>
> On 16-01-17 18:20, Tim Wescott wrote:
>>> The problem to create a digital signal for even the lowest ham-bands
>>> (137 Khz) using DDS, the I/O pin of the lowest bit needs to switch at
>>> 35.6 Mhz (if using a nice 8bit DDS). For higher bands, the problem is
>>> even worse, or I need to reduce the resolution of the DDS
>>
>> How are you arriving at that number?  In a world where perfect
>> reconstruction filters exist, you can run the output frequency all the
>> way up to half of the clock frequency.  If you want to make the
>> reconstruction filtering much easier you'd limit the output to something
>> like Fs/4 -- and 548kHz is a hell of a lot less than 35.6MHz.
>>
>> This article should help to clarify your thinking:
>> http://wescottdesign.com/articles/Sampling/sampling.pdf
>
> Thanks for the link. (actually quite an interesting read) :-)
>
>
>
>> As for your question about I/O rates: probably up to hundreds of MHz, but
>> it somewhat depends on your abilities.  If you don't want to spread your
>> output spectrum from the DDS you may want to make a stable clock source
>> external of the FPGA and use that both to drive the DAC's sample clock
>> and the FPGA.  At least the last time I checked (which, granted, was 20
>> years ago), internal FPGA circuitry was too noisy to use as sampling
>> clocks in communications applications.
>
> That is interesting information. Thanks. :-)
>
>
> Again thanks to you and to all who replied.
>
> As said, currently this is just an exercise for myself, but the goal
> does is to actually build this thing: get the analog backend of the this
> done correctly and use it -as a portable FSK31-enabled beacon-, perhaps
> for SOTA-operations.

Ok, so some things have been explained more clearly, other things are 
more muddy.

All the stuff about the PSK31 signal and other background is fine, but 
not terribly important to what you need from us.

You are asking how fast an FPGA I/O can be switched which I think is 
also not terribly relevant to your real problem, but I believe someone 
answered that... "it depends".

An I/O in an FPGA typically is programmable both in drive strength and 
in slew rate.  This is to allow support of multiple I/O standards while 
also allowing a minimum of RF interference being created by the digital 
outputs.  Very fast edges create high frequency harmonics.  Slower edges 
reduce these harmonics.  So this setting ultimately sets the limit to 
how fast you can switch an I/O pin.  However, FPGAs are intended to be 
synchronously clocked devices, so usually what is more important is the 
internal maximum clock rate which will set the maximum rate for changing 
the value driven to the I/O pin.  This is specified in most FPGA data 
sheets, but does not reflect a terribly useful parameter when the FPGA 
is doing much logic work.  This logic slows the maximum clock rate and 
so the I/O toggle rate in any useful design.

Now, to the DDS.  A DDS is typically designed with two sections, a phase 
accumulator and a sine generator.  The phase accumulator does not always 
count by one.  It can be programmable with a variable step size to 
generate a variable frequency sine wave from a fixed frequency digital 
clock.  The formula is Fout = Fclk * N / M where Fclk is the digital 
clock rate, N is the step size added to the phase accumulator on each 
clock and M is the modulus of the phase accumulator which does not have 
to be a binary number.  It is only important that the counter count from 
0 to M-1 and then wrap around to 0 again.

What is not clear to me is if the PSK31 signal is a PSK31 modulated 
audio tone that is then modulated on a carrier, or if the carrier is 
directly modulated with PSK31.  The articles I've seen talk about using 
a PC sound card output to generate the audio signal but they don't say 
how this is modulated on the carrier... perhaps I'm showing my ignorance 
of ham radio.  lol

The design of a directly modulated PSK31 signal at RF means you will 
generate a carrier, but it needs to be modulated both in phase and 
amplitude.  I don't know how they accomplished that in the article you 
read, but in the FPGA the phase modulation is just an increment that is 
added to the output of the phase accumulator in the DDS, equal to half 
the modulus M of the accumulator (180 degrees).  The amplitude would be 
adjusted by a multiplier after the sine wave generator.

BTW, in an FPGA there is no reason to limit yourself to a 256 entry look 
up table (LUT) for the sine wave generator.  There are also shortcuts 
you can use to cut the size of this table by 4.  So using a 2048 entry 
table you can use 8192 points per cycle of the sine wave.  These take 
advantage of the redundancy of the values in a sine wave cycle, ramping 
up vs ramping down and positive values vs. negative values.  You also 
don't even need to use a LUT.  There are approximations using multiplies 
that can get you 18 bits of resolution on the input to the sine 
generator.  This reduces what is called phase truncation which creates 
close in spurs to the carrier which are hard to filter out.  More phase 
resolution reduces these spurs and gives you a cleaner signal.

I spent some time looking at DDS designs in FPGAs and found that most 
designs stop well short of squeezing the best performance available.

-- 

Rick C