Sensor data length is 16 bit data, value is from -32768 to 32767,i think data format represented as one highest is sign and others are integers, who can help how to convert it to Q15 data format in VHDL? Q15 like https://en.wikipedia.org/wiki/Q_(number_format) one sigh and others are fractional from -1 to 1 Sensor is ADC output is 16 bit format, one sign and other integer so it need only divide ? ADC output to 32768 ??
VHDL, how to convert sensor data to Q15
Started by ●January 21, 2017
Reply by ●January 21, 20172017-01-21
On Sat, 21 Jan 2017 07:58:02 -0800, abirov wrote:> Sensor data length is 16 bit data, value is from -32768 to 32767,i think > data format represented as one highest is sign and others are integers, > who can help how to convert it to Q15 data format in VHDL? > > Q15 like https://en.wikipedia.org/wiki/Q_(number_format) one sigh and > others are fractional from -1 to 1 > > Sensor is ADC output is 16 bit format, one sign and other integer > > so it need only divide ? ADC output to 32768 ??OK. First, in an FPGA, if you're going to start with 16 bits and end up with 16 bits and divide by 32768, what do you need to do other than relabel the bits? Second, review your number formats very carefully. I strongly suspect that everything is in 2's compliment where, indeed, the MSB is the sign bit, but things are more complicated than that. As far as I know, if it's called Q15, it's just 2's compliment integer shifted down by 15 bits. Third, verify what the ADC is putting out. Some put out 2's compliment, some put out straight binary, and it's up to you to invert the first bit to get 2's compliment. -- Tim Wescott Control systems, embedded software and circuit design I'm looking for work! See my website if you're interested http://www.wescottdesign.com
Reply by ●January 21, 20172017-01-21
Den lørdag den 21. januar 2017 kl. 17.38.01 UTC+1 skrev Tim Wescott:> On Sat, 21 Jan 2017 07:58:02 -0800, abirov wrote: > > > Sensor data length is 16 bit data, value is from -32768 to 32767,i think > > data format represented as one highest is sign and others are integers, > > who can help how to convert it to Q15 data format in VHDL? > > > > Q15 like https://en.wikipedia.org/wiki/Q_(number_format) one sigh and > > others are fractional from -1 to 1 > > > > Sensor is ADC output is 16 bit format, one sign and other integer > > > > so it need only divide ? ADC output to 32768 ?? > > OK. First, in an FPGA, if you're going to start with 16 bits and end up > with 16 bits and divide by 32768, what do you need to do other than > relabel the bits? > > Second, review your number formats very carefully. I strongly suspect > that everything is in 2's compliment where, indeed, the MSB is the sign > bit, but things are more complicated than that. As far as I know, if > it's called Q15, it's just 2's compliment integer shifted down by 15 bits. > > Third, verify what the ADC is putting out. Some put out 2's compliment, > some put out straight binary, and it's up to you to invert the first bit > to get 2's compliment. >yes it is just a relabeling until you start multiplying. 1.15 * 1.15 results in 2.30 to get back to 1.15 you need skip an msb and use the upper bits (and keep in mind the -1*-1 results in overflow) -Lasse
Reply by ●January 21, 20172017-01-21
On Sat, 21 Jan 2017 09:14:18 -0800, lasselangwadtchristensen wrote:> Den lørdag den 21. januar 2017 kl. 17.38.01 UTC+1 skrev Tim Wescott: >> On Sat, 21 Jan 2017 07:58:02 -0800, abirov wrote: >> >> > Sensor data length is 16 bit data, value is from -32768 to 32767,i >> > think data format represented as one highest is sign and others are >> > integers, who can help how to convert it to Q15 data format in VHDL? >> > >> > Q15 like https://en.wikipedia.org/wiki/Q_(number_format) one sigh and >> > others are fractional from -1 to 1 >> > >> > Sensor is ADC output is 16 bit format, one sign and other integer >> > >> > so it need only divide ? ADC output to 32768 ?? >> >> OK. First, in an FPGA, if you're going to start with 16 bits and end >> up with 16 bits and divide by 32768, what do you need to do other than >> relabel the bits? >> >> Second, review your number formats very carefully. I strongly suspect >> that everything is in 2's compliment where, indeed, the MSB is the sign >> bit, but things are more complicated than that. As far as I know, if >> it's called Q15, it's just 2's compliment integer shifted down by 15 >> bits. >> >> Third, verify what the ADC is putting out. Some put out 2's >> compliment, some put out straight binary, and it's up to you to invert >> the first bit to get 2's compliment. >> >> > yes it is just a relabeling until you start multiplying. > > 1.15 * 1.15 results in 2.30 to get back to 1.15 you need skip an msb and > use the upper bits (and keep in mind the -1*-1 results in overflow) > > -LasseI wrote my own set of Q15 and Q31 code (software, not HDL) that travels around with me. Even though it takes a few clock ticks on every operation, I simply forbid 0x80..0 -- it makes life ever so much simpler. Dunno how hard it'd be with an FPGA, but it might be worthwhile. -- Tim Wescott Control systems, embedded software and circuit design I'm looking for work! See my website if you're interested http://www.wescottdesign.com
Reply by ●January 21, 20172017-01-21
On 1/21/2017 10:58 AM, abirov@gmail.com wrote:> Sensor data length is 16 bit data, value is from -32768 to 32767,i think data format represented as one highest is sign and others are integers, who can help how to convert it to Q15 data format in VHDL? > > Q15 like https://en.wikipedia.org/wiki/Q_(number_format) one sigh and others are fractional from -1 to 1 > > Sensor is ADC output is 16 bit format, one sign and other integer > > so it need only divide ? ADC output to 32768 ??As others have indicated, there is no logic required to convert between the two formats. Here are some links for the proposed IEEE fixed point arithmetic package. http://wayback.archive.org/web/20151124101646/http://www.vhdl.org/fphdl/Fixed_ug.pdf http://wayback.archive.org/web/20151130082614/http://vhdl.org/fphdl/fixed_pkg_c.vhdl -- Rick C
Reply by ●January 21, 20172017-01-21
On 1/21/2017 5:25 PM, rickman wrote:> On 1/21/2017 10:58 AM, abirov@gmail.com wrote: >> Sensor data length is 16 bit data, value is from -32768 to 32767,i >> think data format represented as one highest is sign and others are >> integers, who can help how to convert it to Q15 data format in VHDL? >> >> Q15 like https://en.wikipedia.org/wiki/Q_(number_format) one sigh and >> others are fractional from -1 to 1 >> >> Sensor is ADC output is 16 bit format, one sign and other integer >> >> so it need only divide ? ADC output to 32768 ?? > > As others have indicated, there is no logic required to convert between > the two formats. Here are some links for the proposed IEEE fixed point > arithmetic package. > > http://wayback.archive.org/web/20151124101646/http://www.vhdl.org/fphdl/Fixed_ug.pdf > > > http://wayback.archive.org/web/20151130082614/http://vhdl.org/fphdl/fixed_pkg_c.vhdlAnd you might need this one too. http://wayback.archive.org/web/20160129055142/http://www.vhdl.org/fphdl/fixed_float_types_c.vhdl -- Rick C
Reply by ●January 22, 20172017-01-22
On 21/01/2017 22:26, rickman wrote:> On 1/21/2017 5:25 PM, rickman wrote:..>> >> As others have indicated, there is no logic required to convert between >> the two formats. Here are some links for the proposed IEEE fixed point >> arithmetic package. >> >> http://wayback.archive.org/web/20151124101646/http://www.vhdl.org/fphdl/Fixed_ug.pdf >> >> >> >> http://wayback.archive.org/web/20151130082614/http://vhdl.org/fphdl/fixed_pkg_c.vhdl >> > > And you might need this one too. > > http://wayback.archive.org/web/20160129055142/http://www.vhdl.org/fphdl/fixed_float_types_c.vhdl > >Bit of extra info, I would not compile these packages yourself but use the ones supplied with your simulator as they are most likely tuned for some extra performance. In Modelsim you can find the precompiled library in <install_dir>\floatfixlib and the source files in <install_dir>\vhdl_src\floatfixlib. Good luck, Hans www.ht-lab.com
Reply by ●February 3, 20172017-02-03
It is too complicated to understand to me,I just want to divide range of numbers from -32767 to +32767 and get according data from -1 to +1. To get this i must divide by 32767. For this purpose i use Xilinx divider generator.So i use signed core, reminder type both fractional and reminder too. It is OK when results must be 1 or more,but when it less then 1 thats sad. When result must be more then 1 quotient show right results in two's compliment digits (according to datasheet) . But !!! fractional part is mad, cannot use two's compliment digit conversion. when i divide any digit to 32767 (0111111111111111) and in fractional result is always dividend. I tryed fractional part 32-bit width but no result/ Why it doesnot work ? Does anyone meet this problem ?
Reply by ●February 3, 20172017-02-03
On Fri, 03 Feb 2017 07:32:52 -0800, abirov wrote:> It is too complicated to understand to me,I just want to divide range of > numbers from -32767 to +32767 and get according data from -1 to +1. To > get this i must divide by 32767. > > For this purpose i use Xilinx divider generator.So i use signed core, > reminder type both fractional and reminder too. > > It is OK when results must be 1 or more,but when it less then 1 thats > sad. > When result must be more then 1 quotient show right results in two's > compliment digits (according to datasheet) . But !!! fractional part is > mad, cannot use two's compliment digit conversion. when i divide any > digit to 32767 (0111111111111111) and in fractional result is always > dividend. I tryed fractional part 32-bit width but no result/ > > Why it doesnot work ? Does anyone meet this problem ?Explain how it is "mad". And please, please, please, stop for a moment and think on how sensible it is to use up a whole bunch of resources to do a divide by 32767 when a divide by 32768 is just a matter of shifting down by 16 bits -- which, on an FPGA, is simply a matter of relabeling your wires. If you're absolutely bound and determined to divide by 32767, then use the following rule, which shouldn't take too much logic, because if you think about it you'll only be paying attention to the top two bits: * If the input number has an absolute value less than 0x4000, shift down by 16 * If the input number has an absolute value 0x4000 or greater, shift down by 16 and add (or subtract) 1 to (from) it, depending on whether it's positive or negative. * Unless, of course, the input is 32767, in which case you need to shift down by 16 and _don't_ add 1, because if you do the result will be -1, which is a lot different from 1 - 1/32768. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com I'm looking for work -- see my website!
Reply by ●February 6, 20172017-02-06