Verilog vs VHDL for Loops

Andre Bonin a �crit:
> Ken McElvain wrote:
> 
>> This loop should compile fine in Synplify.
> 
> 
> I'me using quartus2.  What is synplify?

QuertusII doesn't like VHDL while loops. I replaced one with a for loop 
and an exit statement and it worked OK.
I don't know if it is the same with Verilog while loops though.


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Nicolas Matringe <nicolasmatringe001@numeri-cable.fr> wrote in message news:<414FD415.5080508@numeri-cable.fr>...
> Andre Bonin a &#4294967295;crit:
> > Ken McElvain wrote:
> > 
> >> This loop should compile fine in Synplify.
> > 
> > 
> > I'me using quartus2.  What is synplify?
> 
> QuertusII doesn't like VHDL while loops. I replaced one with a for loop 
> and an exit statement and it worked OK.
> I don't know if it is the same with Verilog while loops though.

I haven't used Synplify in ages, but I use Precision all the time. 
According to the Precision manual, "Loops must be bounded by constants
or contain [a] @(posedge clk) statement."

The original poster's code:

    integer X = 0;
    always begin
        while (X < 30) begin
           X = X + 1;
        end // while
    end // always

has a couple of problems.  First, if one were to simulate this, one
would see that it actually would execute in zero time.  How SHOULD
this be implemented in hardware?

The initializer is ignored (think about it: what's the synthesizer
supposed to do with it?).  The while statement isn't bounded like the
usual for loop:

    for (x = 0; x < 30; x = x + 1) begin ... end //

Note the constants in that for loop, tho'.  Say you had:

    integer first, last;

    for (x = first; x < last; x = x + 1) begin

those values aren't bounded, either, so the synthesizer wouldn't know
what to do with it.

The manual does say that the two loop conditions are ORed, so it one
modified the original poster's code as follows:

    always @(posedge clk) begin
        while (X < 30) begin
           X = X + 1;
        end // while
    end // always

then one would expect things to "work."  (It's a simple incrementer
that stops when it hits the value 30.  Not very useful unless it can
be reset!)

Think hardware ...

-a

Andre Bonin wrote:
> Ken McElvain wrote:
> 
>> This loop should compile fine in Synplify.
> 
> 
> I'me using quartus2.  What is synplify?

Synplify is a commercial FPGA synthesis tool
See:   http://www.synplicity.com for details.
I'm obviously biased, but I think it is the best FPGA
synthesis tool available.

- Ken

> 
> 
>>
>> Andre Bonin wrote:
>>
>>> Hey all, I'me trying to convert a C algorithm to Verilog using 
>>> Quartus II Web edition.
>>>
>>> The following for loop doesn't compile because it says its not of 
>>> constant loop time.
>>>
>>> What i really need is to be able to calculate the loop time "on the 
>>> fly".
>>>
>>> Can VHDL or Verilog do this? or is this a limitation?
>>>
>>>
>>> Thanks
>>> Error: Verilog HDL For Statement error at XXXXXXXX.v(49): must use 
>>> only constant expressions in terminating conditions
>>>
>>> ---- Error at while loop -
>>>     integer X = 0;
>>>     always
>>>     begin
>>>         while( X < 30 )
>>>         begin
>>>             X = X + 1;
>>>         end
>>>     end
>>
>>
>>

Synplify internally transforms for loops into while
loops for synthesis.   Loops (while or for) without
event controls can be synthesisized as long as the terminating
condition can be determined (this is known as the
halting problem).   Synplify can figure this out for
quite complex loops.   In the example, there is a
problem with the lack of initialization of the variable X
inside the always block that makes it difficult to compute
the termination condition.

Either type of loop, while or for, can also be synthesized
when all paths through the loop are broken by an event
control.

An event control is the @(posedge clk) refered to below.

Andy Peters wrote:

> Nicolas Matringe <nicolasmatringe001@numeri-cable.fr> wrote in message news:<414FD415.5080508@numeri-cable.fr>...
> 
>>Andre Bonin a &#4294967295;crit:
>>
>>>Ken McElvain wrote:
>>>
>>>
>>>>This loop should compile fine in Synplify.
>>>
>>>
>>>I'me using quartus2.  What is synplify?
>>
>>QuertusII doesn't like VHDL while loops. I replaced one with a for loop 
>>and an exit statement and it worked OK.
>>I don't know if it is the same with Verilog while loops though.
> 
> 
> I haven't used Synplify in ages, but I use Precision all the time. 
> According to the Precision manual, "Loops must be bounded by constants
> or contain [a] @(posedge clk) statement."
> 
> The original poster's code:
> 
>     integer X = 0;
>     always begin
>         while (X < 30) begin
>            X = X + 1;
>         end // while
>     end // always
> 
> has a couple of problems.  First, if one were to simulate this, one
> would see that it actually would execute in zero time.  How SHOULD
> this be implemented in hardware?
> 
> The initializer is ignored (think about it: what's the synthesizer
> supposed to do with it?).  The while statement isn't bounded like the
> usual for loop:
> 
>     for (x = 0; x < 30; x = x + 1) begin ... end //
> 
> Note the constants in that for loop, tho'.  Say you had:
> 
>     integer first, last;
> 
>     for (x = first; x < last; x = x + 1) begin
> 
> those values aren't bounded, either, so the synthesizer wouldn't know
> what to do with it.
> 
> The manual does say that the two loop conditions are ORed, so it one
> modified the original poster's code as follows:
> 
>     always @(posedge clk) begin
>         while (X < 30) begin
>            X = X + 1;
>         end // while
>     end // always
> 
> then one would expect things to "work."  (It's a simple incrementer
> that stops when it hits the value 30.  Not very useful unless it can
> be reset!)
> 
> Think hardware ...
> 
> -a