How to make master FPGA to connect to many FPGAs ? Two FPGAs connected by serial TDI - TDO, and two fpgas TMS TCK TDO and TDI connect to master fpga, master fpga has TMS TDI TDO TCK connected and working to pc normally, it need to make connection JTAG of two fpgas to other 4 ports or somehow can connect to master's jtag port ?
Master Xilinx FPGA like Jtag bridge.
Started by ●February 25, 2017
Reply by ●February 25, 20172017-02-25
|---------|-TMS----|------------|-TMS----
| FPGA 0 |-TCK----| |-TCK----
| |-TDO----| |-TDO----
|---------| | |-TDI----
| | |
TDI | |
| | |
| | MASTER FPGA|
| | |
TDO | |
| | |
|---------|-TMS----| |
| FGPA 1 |-TCK----| |
| |-TDI----| |
|---------| |------------|
Reply by ●February 25, 20172017-02-25
On Saturday, February 25, 2017 at 11:21:13 AM UTC+6, abi...@gmail.com wrote:> How to make master FPGA to connect to many FPGAs ? > > Two FPGAs connected by serial TDI - TDO, and two fpgas TMS TCK TDO and TDI connect to master fpga, master fpga has TMS TDI TDO TCK connected and working to pc normally, it need to make connection JTAG of two fpgas to other 4 ports or somehow can connect to master's jtag port ?| |---------|-TMS----|------------|-TMS---- | | FPGA 0 |-TCK----| |-TCK---- | | |-TDO----| |-TDO---- | |---------| | |-TDI---- | | | | | TDI | | | | | | | | | MASTER FPGA| | | | | | TDO | | | | | | | |---------|-TMS----| | | | FGPA 1 |-TCK----| | | | |-TDI----| | | |---------| |------------|
Reply by ●February 25, 20172017-02-25
On 2/25/2017 12:33 AM, abirov@gmail.com wrote:> On Saturday, February 25, 2017 at 11:21:13 AM UTC+6, abi...@gmail.com wrote: >> How to make master FPGA to connect to many FPGAs ? >> >> Two FPGAs connected by serial TDI - TDO, and two fpgas TMS TCK TDO and TDI connect to master fpga, master fpga has TMS TDI TDO TCK connected and working to pc normally, it need to make connection JTAG of two fpgas to other 4 ports or somehow can connect to master's jtag port ? > > | |---------|-TMS----|------------|-TMS---- > | | FPGA 0 |-TCK----| |-TCK---- > | | |-TDO----| |-TDO---- > | |---------| | |-TDI---- > | | | | > | TDI | | > | | | | > | | | MASTER FPGA| > | | | | > | TDO | | > | | | | > | |---------|-TMS----| | > | | FGPA 1 |-TCK----| | > | | |-TDI----| | > | |---------| |------------| >Why do you want the master FPGA to control the others rather than loading them all in one chain? Connect all TMS and TCK lines in parallel and connect all TDI and TDO in one big daisy chain. If the slave FPGAs are loaded by the master, where will the data come from? -- Rick C
Reply by ●February 26, 20172017-02-26
On Saturday, February 25, 2017 at 3:22:21 PM UTC+6, rickman wrote:> On 2/25/2017 12:33 AM, abirov@gmail.com wrote: > > On Saturday, February 25, 2017 at 11:21:13 AM UTC+6, abi...@gmail.com wrote: > >> How to make master FPGA to connect to many FPGAs ? > >> > >> Two FPGAs connected by serial TDI - TDO, and two fpgas TMS TCK TDO and TDI connect to master fpga, master fpga has TMS TDI TDO TCK connected and working to pc normally, it need to make connection JTAG of two fpgas to other 4 ports or somehow can connect to master's jtag port ? > > > > | |---------|-TMS----|------------|-TMS---- > > | | FPGA 0 |-TCK----| |-TCK---- > > | | |-TDO----| |-TDO---- > > | |---------| | |-TDI---- > > | | | | > > | TDI | | > > | | | | > > | | | MASTER FPGA| > > | | | | > > | TDO | | > > | | | | > > | |---------|-TMS----| | > > | | FGPA 1 |-TCK----| | > > | | |-TDI----| | > > | |---------| |------------| > > > > Why do you want the master FPGA to control the others rather than > loading them all in one chain? Connect all TMS and TCK lines in > parallel and connect all TDI and TDO in one big daisy chain. If the > slave FPGAs are loaded by the master, where will the data come from? > > -- > > Rick CIt is reverse engineering, someone did this but i just want reuse board only
Reply by ●February 26, 20172017-02-26
On 2/26/2017 2:27 AM, abirov@gmail.com wrote:> On Saturday, February 25, 2017 at 3:22:21 PM UTC+6, rickman wrote: >> On 2/25/2017 12:33 AM, abirov@gmail.com wrote: >>> On Saturday, February 25, 2017 at 11:21:13 AM UTC+6, abi...@gmail.com wrote: >>>> How to make master FPGA to connect to many FPGAs ? >>>> >>>> Two FPGAs connected by serial TDI - TDO, and two fpgas TMS TCK TDO and TDI connect to master fpga, master fpga has TMS TDI TDO TCK connected and working to pc normally, it need to make connection JTAG of two fpgas to other 4 ports or somehow can connect to master's jtag port ? >>> >>> | |---------|-TMS----|------------|-TMS---- >>> | | FPGA 0 |-TCK----| |-TCK---- >>> | | |-TDO----| |-TDO---- >>> | |---------| | |-TDI---- >>> | | | | >>> | TDI | | >>> | | | | >>> | | | MASTER FPGA| >>> | | | | >>> | TDO | | >>> | | | | >>> | |---------|-TMS----| | >>> | | FGPA 1 |-TCK----| | >>> | | |-TDI----| | >>> | |---------| |------------| >>> >> >> Why do you want the master FPGA to control the others rather than >> loading them all in one chain? Connect all TMS and TCK lines in >> parallel and connect all TDI and TDO in one big daisy chain. If the >> slave FPGAs are loaded by the master, where will the data come from? >> >> -- >> >> Rick C > > It is reverse engineering, someone did this but i just want reuse board onlyThe JTAG signals to the master chip, do they connect to general I/Os as well as to the FPGA JTAG signals? Or just JTAG or just I/Os? You didn't say where you expect the data to come from to program the chained slave FPGAs. Is it supposed to come from the main JTAG port as if it was talking to the slave chain? Or will the master FPGA have a separate interface from an MCU or a Flash chip? What is your overall plan? -- Rick C
Reply by ●March 24, 20172017-03-24
On Sunday, February 26, 2017 at 4:21:49 PM UTC+6, rickman wrote:> On 2/26/2017 2:27 AM, abirov@gmail.com wrote: > > On Saturday, February 25, 2017 at 3:22:21 PM UTC+6, rickman wrote: > >> On 2/25/2017 12:33 AM, abirov@gmail.com wrote: > >>> On Saturday, February 25, 2017 at 11:21:13 AM UTC+6, abi...@gmail.com=wrote:> >>>> How to make master FPGA to connect to many FPGAs ? > >>>> > >>>> Two FPGAs connected by serial TDI - TDO, and two fpgas TMS TCK TDO=and TDI connect to master fpga, master fpga has TMS TDI TDO TCK connected = and working to pc normally, it need to make connection JTAG of two fpgas to= other 4 ports or somehow can connect to master's jtag port ?> >>> > >>> | |---------|-TMS----|------------|-TMS---- > >>> | | FPGA 0 |-TCK----| |-TCK---- > >>> | | |-TDO----| |-TDO---- > >>> | |---------| | |-TDI---- > >>> | | | | > >>> | TDI | | > >>> | | | | > >>> | | | MASTER FPGA| > >>> | | | | > >>> | TDO | | > >>> | | | | > >>> | |---------|-TMS----| | > >>> | | FGPA 1 |-TCK----| | > >>> | | |-TDI----| | > >>> | |---------| |------------| > >>> > >> > >> Why do you want the master FPGA to control the others rather than > >> loading them all in one chain? Connect all TMS and TCK lines in > >> parallel and connect all TDI and TDO in one big daisy chain. If the > >> slave FPGAs are loaded by the master, where will the data come from? > >> > >> -- > >> > >> Rick C > > > > It is reverse engineering, someone did this but i just want reuse board=only>=20 > The JTAG signals to the master chip, do they connect to general I/Os as==20> well as to the FPGA JTAG signals? Or just JTAG or just I/Os? >=20 > You didn't say where you expect the data to come from to program the=20 > chained slave FPGAs. Is it supposed to come from the main JTAG port as==20> if it was talking to the slave chain? Or will the master FPGA have a=20 > separate interface from an MCU or a Flash chip? >=20 > What is your overall plan? >=20 > --=20 >=20 > Rick CHi, i am also doing same thing and also have same question )))). I think fi= rst need program master FPGA and then normal masters JTAG can be used as JT= AG for other tributary fpgas . may be/
Reply by ●March 24, 20172017-03-24
On Sunday, February 26, 2017 at 4:21:49 PM UTC+6, rickman wrote:> On 2/26/2017 2:27 AM, abirov@gmail.com wrote: > > On Saturday, February 25, 2017 at 3:22:21 PM UTC+6, rickman wrote: > >> On 2/25/2017 12:33 AM, abirov@gmail.com wrote: > >>> On Saturday, February 25, 2017 at 11:21:13 AM UTC+6, abi...@gmail.com wrote: > >>>> How to make master FPGA to connect to many FPGAs ? > >>>> > >>>> Two FPGAs connected by serial TDI - TDO, and two fpgas TMS TCK TDO and TDI connect to master fpga, master fpga has TMS TDI TDO TCK connected and working to pc normally, it need to make connection JTAG of two fpgas to other 4 ports or somehow can connect to master's jtag port ? > >>> > >>> | |---------|-TMS----|------------|-TMS---- > >>> | | FPGA 0 |-TCK----| |-TCK---- > >>> | | |-TDO----| |-TDO---- > >>> | |---------| | |-TDI---- > >>> | | | | > >>> | TDI | | > >>> | | | | > >>> | | | MASTER FPGA| > >>> | | | | > >>> | TDO | | > >>> | | | | > >>> | |---------|-TMS----| | > >>> | | FGPA 1 |-TCK----| | > >>> | | |-TDI----| | > >>> | |---------| |------------| > >>> > >> > >> Why do you want the master FPGA to control the others rather than > >> loading them all in one chain? Connect all TMS and TCK lines in > >> parallel and connect all TDI and TDO in one big daisy chain. If the > >> slave FPGAs are loaded by the master, where will the data come from? > >> > >> -- > >> > >> Rick C > > > > It is reverse engineering, someone did this but i just want reuse board only > > The JTAG signals to the master chip, do they connect to general I/Os as > well as to the FPGA JTAG signals? Or just JTAG or just I/Os? > > You didn't say where you expect the data to come from to program the > chained slave FPGAs. Is it supposed to come from the main JTAG port as > if it was talking to the slave chain? Or will the master FPGA have a > separate interface from an MCU or a Flash chip? > > What is your overall plan? > > -- > > Rick CSlave FPGAs connects to USER I/O ports. for example: TMS of salve FPGA chip connects to user i/o pin CC TDI of slave FPGA chip connects to user i/0 pin VRP TCK of slave FPGA ship connects to user i/o pin CC
Reply by ●March 24, 20172017-03-24
On 3/24/2017 7:30 AM, jelloaman@gmail.com wrote:> On Sunday, February 26, 2017 at 4:21:49 PM UTC+6, rickman wrote: >> On 2/26/2017 2:27 AM, abirov@gmail.com wrote: >>> On Saturday, February 25, 2017 at 3:22:21 PM UTC+6, rickman wrote: >>>> On 2/25/2017 12:33 AM, abirov@gmail.com wrote: >>>>> On Saturday, February 25, 2017 at 11:21:13 AM UTC+6, abi...@gmail.com wrote: >>>>>> How to make master FPGA to connect to many FPGAs ? >>>>>> >>>>>> Two FPGAs connected by serial TDI - TDO, and two fpgas TMS TCK TDO and TDI connect to master fpga, master fpga has TMS TDI TDO TCK connected and working to pc normally, it need to make connection JTAG of two fpgas to other 4 ports or somehow can connect to master's jtag port ? >>>>> >>>>> | |---------|-TMS----|------------|-TMS---- >>>>> | | FPGA 0 |-TCK----| |-TCK---- >>>>> | | |-TDO----| |-TDO---- >>>>> | |---------| | |-TDI---- >>>>> | | | | >>>>> | TDI | | >>>>> | | | | >>>>> | | | MASTER FPGA| >>>>> | | | | >>>>> | TDO | | >>>>> | | | | >>>>> | |---------|-TMS----| | >>>>> | | FGPA 1 |-TCK----| | >>>>> | | |-TDI----| | >>>>> | |---------| |------------| >>>>> >>>> >>>> Why do you want the master FPGA to control the others rather than >>>> loading them all in one chain? Connect all TMS and TCK lines in >>>> parallel and connect all TDI and TDO in one big daisy chain. If the >>>> slave FPGAs are loaded by the master, where will the data come from? >>>> >>>> -- >>>> >>>> Rick C >>> >>> It is reverse engineering, someone did this but i just want reuse board only >> >> The JTAG signals to the master chip, do they connect to general I/Os as >> well as to the FPGA JTAG signals? Or just JTAG or just I/Os? >> >> You didn't say where you expect the data to come from to program the >> chained slave FPGAs. Is it supposed to come from the main JTAG port as >> if it was talking to the slave chain? Or will the master FPGA have a >> separate interface from an MCU or a Flash chip? >> >> What is your overall plan? >> >> -- >> >> Rick C > > Slave FPGAs connects to USER I/O ports. for example: > TMS of salve FPGA chip connects to user i/o pin CC > TDI of slave FPGA chip connects to user i/0 pin VRP > TCK of slave FPGA ship connects to user i/o pin CCWhat do you connect the user I/O of the master to internally? If you try using the JTAG on the master it will control the master, no? -- Rick C
Reply by ●March 24, 20172017-03-24
>>>>>>> How to make master FPGA to connect to many FPGAs ? >>>>>>> >>>>>>> Two FPGAs connected by serial TDI - TDO, and two fpgas TMS TCK >>>>>>> TDO and TDI connect to master fpga, master fpga has TMS TDI TDO >>>>>>> TCK connected and working to pc normally, it need to make >>>>>>> connection JTAG of two fpgas to other 4 ports or somehow can >>>>>>> connect to master's jtag port ? >>>>>> >>>>>> | |---------|-TMS----|------------|-TMS---- >>>>>> | | FPGA 0 |-TCK----| |-TCK---- >>>>>> | | |-TDO----| |-TDO---- >>>>>> | |---------| | |-TDI---- >>>>>> | | | | >>>>>> | TDI | | >>>>>> | | | | >>>>>> | | | MASTER FPGA| >>>>>> | | | | >>>>>> | TDO | | >>>>>> | | | | >>>>>> | |---------|-TMS----| | >>>>>> | | FGPA 1 |-TCK----| | >>>>>> | | |-TDI----| | >>>>>> | |---------| |------------| >>>>>> >>>>> >>>>> Why do you want the master FPGA to control the others rather than >>>>> loading them all in one chain? Connect all TMS and TCK lines in >>>>> parallel and connect all TDI and TDO in one big daisy chain. If the >>>>> slave FPGAs are loaded by the master, where will the data come from? >>>> It is reverse engineering, someone did this but i just want reuse >>>> board only >>> >>> The JTAG signals to the master chip, do they connect to general I/Os as >>> well as to the FPGA JTAG signals? Or just JTAG or just I/Os? >>> >>> You didn't say where you expect the data to come from to program the >>> chained slave FPGAs. Is it supposed to come from the main JTAG port as >>> if it was talking to the slave chain? Or will the master FPGA have a >>> separate interface from an MCU or a Flash chip? >>> >>> What is your overall plan? >> Slave FPGAs connects to USER I/O ports. for example: >> TMS of salve FPGA chip connects to user i/o pin CC >> TDI of slave FPGA chip connects to user i/0 pin VRP >> TCK of slave FPGA ship connects to user i/o pin CC > > What do you connect the user I/O of the master to internally? If you > try using the JTAG on the master it will control the master, no? >Perhaps you are looking for something similar like Altera JAM Player for embedded. Take a look here https://www.altera.com/support/support-resources/support-centers/devices/programming-tools/jam-stapl/tls-jam-embedded.html There is pice of C code able to send chip image from embedded system to another fpga. Unfortunatell I don't know X as good as I would like to. BR Adam
