I don't know where to ask this, so I'll try here. Are analog to digital converters fundamentally, in their core inner design, basically tiny systems which operate like 555 timers, with a series of resistors and capacitors designed to sample ranges, essentially counting ticks per fixed units of time, resulting in the digital data necessary to perform an indexed lookup from the inner sampler that's in range, to produce an output bit patfern? With then some tail logic to prevent jitter beyond an expected operating range / frequency? Thank you, Rick C. Hodgin
Analog to digital converters
Started by ●March 9, 2017
Reply by ●March 9, 20172017-03-09
On 09/03/2017 09:46, Rick C. Hodgin wrote:> I don't know where to ask this, so I'll try here. > > Are analog to digital converters fundamentally, in their core inner > design, basically tiny systems which operate like 555 timers, with a > series of resistors and capacitors designed to sample ranges, essentially > counting ticks per fixed units of time, resulting in the digital data > necessary to perform an indexed lookup from the inner sampler > that's in range, to produce an output bit patfern? With then > some tail logic to prevent jitter beyond an expected operating > range / frequency? > > Thank you, > Rick C. Hodgin >There are several designs. Why not start with the obvious place... https://en.wikipedia.org/wiki/Analog-to-digital_converter for an over view of the varios techniques.. Dave
Reply by ●March 9, 20172017-03-09
Thank you. I like to figure things out. And as these ideas occur to me, I like to see if I'm correct. Wikipedia locks up my Dolphin web browser. :-( Thank you, Rick C. Hodgin
Reply by ●March 9, 20172017-03-09
On Thursday, March 9, 2017 at 5:59:27 AM UTC-5, David Wade wrote:> On 09/03/2017 09:46, Rick C. Hodgin wrote: > > Are analog to digital converters fundamentally, in their core inner > > design, basically tiny systems which operate like 555 timers, with a > > series of resistors and capacitors designed to sample ranges, essentially > > counting ticks per fixed units of time, resulting in the digital data > > necessary to perform an indexed lookup from the inner sampler > > that's in range, to produce an output bit patfern? With then > > some tail logic to prevent jitter beyond an expected operating > > range / frequency? > > There are several designs. Why not start with the obvious place... > > https://en.wikipedia.org/wiki/Analog-to-digital_converter > > for an over view of the varios techniques..I was able to look at it on my desktop computer. Thank you for the assistance. :-) Thank you, Rick C. Hodgin
Reply by ●March 9, 20172017-03-09
On 09/03/17 14:46, Rick C. Hodgin wrote:> On Thursday, March 9, 2017 at 5:59:27 AM UTC-5, David Wade wrote: >> On 09/03/2017 09:46, Rick C. Hodgin wrote: >>> Are analog to digital converters fundamentally, in their core inner >>> design, basically tiny systems which operate like 555 timers, with a >>> series of resistors and capacitors designed to sample ranges, essentially >>> counting ticks per fixed units of time, resulting in the digital data >>> necessary to perform an indexed lookup from the inner sampler >>> that's in range, to produce an output bit patfern? With then >>> some tail logic to prevent jitter beyond an expected operating >>> range / frequency? >> >> There are several designs. Why not start with the obvious place... >> >> https://en.wikipedia.org/wiki/Analog-to-digital_converter >> >> for an over view of the varios techniques.. > > I was able to look at it on my desktop computer. Thank you for the > assistance. :-) >You can see there are many methods - none of which fits very well with the description you wrote, as far as I can see. Successive approximation ADC's are the most common for general purpose ADCs. Flash (direct conversion) ADC's are used for very high speed, and Sigma-Delta is the usual method for high resolution (such as audio ADC's).
Reply by ●March 9, 20172017-03-09
David Brown wrote:> On 09/03/17 14:46, Rick C. Hodgin wrote: >> On Thursday, March 9, 2017 at 5:59:27 AM UTC-5, David Wade wrote: >>> On 09/03/2017 09:46, Rick C. Hodgin wrote: >>>> Are analog to digital converters fundamentally, in their core inner >>>> design, basically tiny systems which operate like 555 timers, with a >>>> series of resistors and capacitors designed to sample ranges, essentially >>>> counting ticks per fixed units of time, resulting in the digital data >>>> necessary to perform an indexed lookup from the inner sampler >>>> that's in range, to produce an output bit patfern? With then >>>> some tail logic to prevent jitter beyond an expected operating >>>> range / frequency? >>> There are several designs. Why not start with the obvious place... >>> >>> https://en.wikipedia.org/wiki/Analog-to-digital_converter >>> >>> for an over view of the varios techniques.. >> I was able to look at it on my desktop computer. Thank you for the >> assistance. :-) >> > > You can see there are many methods - none of which fits very well with > the description you wrote, as far as I can see. > > Successive approximation ADC's are the most common for general purpose > ADCs. Flash (direct conversion) ADC's are used for very high speed, and > Sigma-Delta is the usual method for high resolution (such as audio ADC's). > > >Single or Dual-slope integrating ADCs (very slow) are more like the 555 timer approach (if I understand the OP correctly). These are used where speed of conversion is not important, but high resolution and noise immunity are. You might find them in a digital multimeter. I used one in a blood chemistry analyzer. Single-slope is less common. Dual slope works by integrating up on a reference input (constant up slope), then down using the input signal (variable down slope. The time to integrate down to the low threshold is measured to give the ADC output. The up integration time is fixed (there is no high threshold). This allows the output value to be independant of the integrating capacitor value as long as the cap is large enough to prevent saturation during ramp up. -- Gabor
Reply by ●March 9, 20172017-03-09
GaborSzakacs wrote:> David Brown wrote: >> On 09/03/17 14:46, Rick C. Hodgin wrote: >>> On Thursday, March 9, 2017 at 5:59:27 AM UTC-5, David Wade wrote: >>>> On 09/03/2017 09:46, Rick C. Hodgin wrote: >>>>> Are analog to digital converters fundamentally, in their core inner >>>>> design, basically tiny systems which operate like 555 timers, with a >>>>> series of resistors and capacitors designed to sample ranges, >>>>> essentially >>>>> counting ticks per fixed units of time, resulting in the digital data >>>>> necessary to perform an indexed lookup from the inner sampler >>>>> that's in range, to produce an output bit patfern? With then >>>>> some tail logic to prevent jitter beyond an expected operating >>>>> range / frequency? >>>> There are several designs. Why not start with the obvious place... >>>> >>>> https://en.wikipedia.org/wiki/Analog-to-digital_converter >>>> >>>> for an over view of the varios techniques.. >>> I was able to look at it on my desktop computer. Thank you for the >>> assistance. :-) >>> >> >> You can see there are many methods - none of which fits very well with >> the description you wrote, as far as I can see. >> >> Successive approximation ADC's are the most common for general purpose >> ADCs. Flash (direct conversion) ADC's are used for very high speed, and >> Sigma-Delta is the usual method for high resolution (such as audio >> ADC's). >> >> >> > > Single or Dual-slope integrating ADCs (very slow) are more like the > 555 timer approach (if I understand the OP correctly). These are > used where speed of conversion is not important, but high resolution > and noise immunity are. You might find them in a digital multimeter. > I used one in a blood chemistry analyzer. Single-slope is less common. > Dual slope works by integrating up on a reference input (constant up > slope), then down using the input signal (variable down slope. The > time to integrate down to the low threshold is measured to give the > ADC output. The up integration time is fixed (there is no high > threshold). This allows the output value to be independant of the > integrating capacitor value as long as the cap is large enough to > prevent saturation during ramp up. >Oops! I got that backwards. Up slope is fixed time but rate is based on the input signal. Down slope is fixed rate set by a reference and time is measured to get ADC value. The way I originally described it would end up with a 1/x factor in the conversion value. In either case, the circuitry is quite simple since the control logic is mostly a big counter. The timing is generally provided externally, as is the integrating capacitor, which can be quite large and generally wants to be polypropylene or similar dielectric to reduce effects of surface charge storage (rebound). Last time I used one of these was back in the early 1980's. -- Gabor
Reply by ●March 9, 20172017-03-09
GaborSzakacs wrote:> GaborSzakacs wrote: >> David Brown wrote: >>> On 09/03/17 14:46, Rick C. Hodgin wrote: >>>> On Thursday, March 9, 2017 at 5:59:27 AM UTC-5, David Wade wrote: >>>>> On 09/03/2017 09:46, Rick C. Hodgin wrote: >>>>>> Are analog to digital converters fundamentally, in their core inner >>>>>> design, basically tiny systems which operate like 555 timers, with a >>>>>> series of resistors and capacitors designed to sample ranges, >>>>>> essentially >>>>>> counting ticks per fixed units of time, resulting in the digital data >>>>>> necessary to perform an indexed lookup from the inner sampler >>>>>> that's in range, to produce an output bit patfern? With then >>>>>> some tail logic to prevent jitter beyond an expected operating >>>>>> range / frequency? >>>>> There are several designs. Why not start with the obvious place... >>>>> >>>>> https://en.wikipedia.org/wiki/Analog-to-digital_converter >>>>> >>>>> for an over view of the varios techniques.. >>>> I was able to look at it on my desktop computer. Thank you for the >>>> assistance. :-) >>>> >>> >>> You can see there are many methods - none of which fits very well with >>> the description you wrote, as far as I can see. >>> >>> Successive approximation ADC's are the most common for general purpose >>> ADCs. Flash (direct conversion) ADC's are used for very high speed, and >>> Sigma-Delta is the usual method for high resolution (such as audio >>> ADC's). >>> >>> >>> >> >> Single or Dual-slope integrating ADCs (very slow) are more like the >> 555 timer approach (if I understand the OP correctly). These are >> used where speed of conversion is not important, but high resolution >> and noise immunity are. You might find them in a digital multimeter. >> I used one in a blood chemistry analyzer. Single-slope is less common. >> Dual slope works by integrating up on a reference input (constant up >> slope), then down using the input signal (variable down slope. The >> time to integrate down to the low threshold is measured to give the >> ADC output. The up integration time is fixed (there is no high >> threshold). This allows the output value to be independant of the >> integrating capacitor value as long as the cap is large enough to >> prevent saturation during ramp up. >> > > Oops! I got that backwards. Up slope is fixed time but rate is > based on the input signal. Down slope is fixed rate set by a reference > and time is measured to get ADC value. The way I originally described > it would end up with a 1/x factor in the conversion value. In either > case, the circuitry is quite simple since the control logic is mostly > a big counter. The timing is generally provided externally, as > is the integrating capacitor, which can be quite large and generally > wants to be polypropylene or similar dielectric to reduce effects > of surface charge storage (rebound). > > Last time I used one of these was back in the early 1980's. >Here's a data sheet link for a more recent dual-slope ADC chip. It's a bit fancier than the one we had in the 1980's but the main idea is the same: http://ww1.microchip.com/downloads/en/DeviceDoc/21456D.pdf -- Gabor
Reply by ●March 9, 20172017-03-09
On 3/9/2017 4:49 PM, GaborSzakacs wrote:> GaborSzakacs wrote: >> GaborSzakacs wrote: >>> David Brown wrote: >>>> On 09/03/17 14:46, Rick C. Hodgin wrote: >>>>> On Thursday, March 9, 2017 at 5:59:27 AM UTC-5, David Wade wrote: >>>>>> On 09/03/2017 09:46, Rick C. Hodgin wrote: >>>>>>> Are analog to digital converters fundamentally, in their core inner >>>>>>> design, basically tiny systems which operate like 555 timers, with a >>>>>>> series of resistors and capacitors designed to sample ranges, >>>>>>> essentially >>>>>>> counting ticks per fixed units of time, resulting in the digital >>>>>>> data >>>>>>> necessary to perform an indexed lookup from the inner sampler >>>>>>> that's in range, to produce an output bit patfern? With then >>>>>>> some tail logic to prevent jitter beyond an expected operating >>>>>>> range / frequency? >>>>>> There are several designs. Why not start with the obvious place... >>>>>> >>>>>> https://en.wikipedia.org/wiki/Analog-to-digital_converter >>>>>> >>>>>> for an over view of the varios techniques.. >>>>> I was able to look at it on my desktop computer. Thank you for the >>>>> assistance. :-) >>>>> >>>> >>>> You can see there are many methods - none of which fits very well with >>>> the description you wrote, as far as I can see. >>>> >>>> Successive approximation ADC's are the most common for general purpose >>>> ADCs. Flash (direct conversion) ADC's are used for very high speed, >>>> and >>>> Sigma-Delta is the usual method for high resolution (such as audio >>>> ADC's). >>>> >>>> >>>> >>> >>> Single or Dual-slope integrating ADCs (very slow) are more like the >>> 555 timer approach (if I understand the OP correctly). These are >>> used where speed of conversion is not important, but high resolution >>> and noise immunity are. You might find them in a digital multimeter. >>> I used one in a blood chemistry analyzer. Single-slope is less common. >>> Dual slope works by integrating up on a reference input (constant up >>> slope), then down using the input signal (variable down slope. The >>> time to integrate down to the low threshold is measured to give the >>> ADC output. The up integration time is fixed (there is no high >>> threshold). This allows the output value to be independant of the >>> integrating capacitor value as long as the cap is large enough to >>> prevent saturation during ramp up. >>> >> >> Oops! I got that backwards. Up slope is fixed time but rate is >> based on the input signal. Down slope is fixed rate set by a reference >> and time is measured to get ADC value. The way I originally described >> it would end up with a 1/x factor in the conversion value. In either >> case, the circuitry is quite simple since the control logic is mostly >> a big counter. The timing is generally provided externally, as >> is the integrating capacitor, which can be quite large and generally >> wants to be polypropylene or similar dielectric to reduce effects >> of surface charge storage (rebound). >> >> Last time I used one of these was back in the early 1980's. >> > > Here's a data sheet link for a more recent dual-slope ADC chip. > It's a bit fancier than the one we had in the 1980's but the > main idea is the same: > > http://ww1.microchip.com/downloads/en/DeviceDoc/21456D.pdfOne of the advantages of dual slope conversion is that zero input gives a zero reading. Or do they have a separate offset circuit for this? I know many tout such in their designs. -- Rick C
Reply by ●March 10, 20172017-03-10
rickman wrote:> On 3/9/2017 4:49 PM, GaborSzakacs wrote:[snip]>> Here's a data sheet link for a more recent dual-slope ADC chip. >> It's a bit fancier than the one we had in the 1980's but the >> main idea is the same: >> >> http://ww1.microchip.com/downloads/en/DeviceDoc/21456D.pdf > > One of the advantages of dual slope conversion is that zero input gives > a zero reading. Or do they have a separate offset circuit for this? I > know many tout such in their designs. >The MicroChip part in the link has an additional "auto-zero phase" that removes any offset. See section 3.1.1 in the data sheet. Another advantage for DC measurement is that the conversion is taken on the integral of the input voltage over some fixed time period. This makes it easy to filter out AC noise including power line noise. The the blood chemistry analyzer we used a multiple of the line period (50 or 60 Hz) as the integration time. A sampling time of 0.1 second would remove line-frequency noise from 50 or 60 Hz power. This is useful in a handheld multimeter, where the leads are long and can pick up noise easily. -- Gabor
