Hi all, I need to generate a part of my VHDL project as a VHDL gate level IP, in the goal to protect my generic IP core. In fact, I want to protect my own PCI core before delivering the complet VHDL project. My question: Is this possible to do a VHDL gate level Netlist from XST. Then to remap it in my VHDL project. Then to do a concatenated VHDL file of by project . Then do a new synthesis and P&R with webpack from my concatenate VHDL file. If yes, how is the best way ? Regards, Larry www.amontec.com
VHDL gate level from Xilinx XST
Started by ●September 21, 2004
Reply by ●September 13, 20142014-09-13
>Hi all, > >I need to generate a part of my VHDL project as a VHDL gate level IP, in >the goal to protect my generic IP core. > >In fact, I want to protect my own PCI core before delivering the complet >VHDL project. > >My question: >Is this possible to do a VHDL gate level Netlist from XST. >Then to remap it in my VHDL project. >Then to do a concatenated VHDL file of by project . >Then do a new synthesis and P&R with webpack from my concatenate VHDLfile.> >If yes, how is the best way ? > >Regards, >Larry >www.amontec.com > >Yes, I did it an IP stack (TCP/IP) free project: "The following describes the synthesis of the VHDL IP stack, using xilinx XST. The synthesis is done with the free xilinx tool: Release 10.1.03 - xst. The package was installed on a debian linux distribution running on a co-linux system..." --------------------------------------- Posted through http://www.FPGARelated.com