Hi guys, Does anybody have any idea or any link or code for Additive White Gaussian Noise in VHDL ? Or any body have written it or not ? Also how to generate Random Number's in VHDL? Thanks Rgds Macie
AWGN in VHDL
Started by ●September 9, 2003
Reply by ●September 9, 20032003-09-09
MACEI'S wrote:> Hi guys, > > Does anybody have any idea or any link or code for Additive White > Gaussian Noise in VHDL ? Or any body have written it or not ? > > Also how to generate Random Number's in VHDL? > > > Thanks > > Rgds > > MacieFor random numbers try this package: http://www.janick.bergeron.com/wtb/packages/random1.vhd MPJB
Reply by ●September 10, 20032003-09-10
Hi, Sometimes back I had posted the same query on Random Number Generator(RNG).I am reproducing one of the responses that I received , courtesy, Michael Chan.Hope this helps. " General linear feedback shift register based RNGs are probably the easiest to implement on an FPGA. Below is some code I wrote the other day that generates 32-bit random numbers(based on TT800 RNG). ************************************************************************ library IEEE; use IEEE.STD_LOGIC_1164.all; entity LFSR is port( Clk : in STD_LOGIC; D : in STD_LOGIC; Q : out STD_LOGIC; F : out STD_LOGIC ); end LFSR; architecture LFSR of LFSR is signal SR : STD_LOGIC_VECTOR (25 downto 1); begin process (Clk) begin if Clk'event and Clk = '1' then SR <= D & SR(25 downto 2); end if; end process; Q <= SR(1); F <= SR(8); end LFSR; ************************************************************************ library IEEE; use IEEE.STD_LOGIC_1164.all; entity RNG is port( Reset : in STD_LOGIC; Clock : in STD_LOGIC; InputEnable : in STD_LOGIC; Input : in STD_LOGIC_VECTOR(32 downto 1); Output : out STD_LOGIC_VECTOR(32 downto 1) ); end RNG; architecture RNG of RNG is component LFSR port( Clk : in STD_LOGIC; D : in STD_LOGIC; Q : out STD_LOGIC; F : out STD_LOGIC ); end component; -- magic vectors constant MAG_FEEDBACK : STD_LOGIC_VECTOR := X"8EBFD028"; constant MAG_OUTA : STD_LOGIC_VECTOR := X"2B5B2500"; constant MAG_OUTB : STD_LOGIC_VECTOR := X"DB8B0000"; signal D, F, Q, shifted, feedback : STD_LOGIC_VECTOR(32 downto 1); -- output processing signals signal outa, outb : STD_LOGIC_VECTOR(32 downto 1); begin LFSRs : for i in 32 downto 1 generate ShiftRegister : LFSR port map (Clock, D(i), Q(i), F(i)); end generate; -- twist and feedback shifted <= '0' & Q(32 downto 2); feedback <= (F xor shifted) when (Q(1) = '0') else (F xor shifted xor MAG_FEEDBACK); D <= feedback when InputEnable = '0' else Input; -- produce output outa <= Q xor ((Q(25 downto 1) & B"0000_000") and MAG_OUTA); outb <= outa xor ((outa(17 downto 1) & B"0000_0000_0000_000") and MAG_OUTB); Output <= outb xor (X"0000" & outb(32 downto 17)); end RNG; ************************************************************************ library IEEE; use IEEE.std_logic_1164.all; entity Testbench is end Testbench; architecture Testbench of Testbench is component RNG port (Reset : in STD_LOGIC; Clock : in STD_LOGIC; InputEnable : in STD_LOGIC; Input : in STD_LOGIC_VECTOR; Output : out STD_LOGIC_VECTOR ); end component; signal Reset : STD_LOGIC; signal Clock : STD_LOGIC; signal InputEnable : STD_LOGIC; signal Input, Output : STD_LOGIC_VECTOR (32 downto 1); begin RNG1 : RNG port map (Reset, Clock, InputEnable, Input, Output); -- clock process begin Clock <= '0'; wait for 5 ns; Clock <= '1'; wait for 5 ns; end process; -- reset RNG process begin Reset <= '0'; wait for 2 ns; Reset <= '1'; wait for 10 ns; Reset <= '0'; wait for 10000 ns; end process; -- seed RNG process begin Input <= (others => '0'); InputEnable <= '1'; wait until Clock'Event and Clock = '1' and Reset = '0'; wait for 1 ns; -- seed RNG with any old stuff Input <= X"95f24dab"; wait for 10 ns; Input <= X"0b685215"; wait for 10 ns; Input <= X"e76ccae7"; wait for 10 ns; Input <= X"af3ec239"; wait for 10 ns; Input <= X"715fad23"; wait for 10 ns; Input <= X"24a590ad"; wait for 10 ns; Input <= X"69e4b5ef"; wait for 10 ns; Input <= X"bf456141"; wait for 10 ns; Input <= X"96bc1b7b"; wait for 10 ns; Input <= X"a7bdf825"; wait for 10 ns; Input <= X"c1de75b7"; wait for 10 ns; Input <= X"8858a9c9"; wait for 10 ns; Input <= X"2da87693"; wait for 10 ns; Input <= X"b657f9dd"; wait for 10 ns; Input <= X"ffdc8a9f"; wait for 10 ns; Input <= X"8121da71"; wait for 10 ns; Input <= X"8b823ecb"; wait for 10 ns; Input <= X"885d05f5"; wait for 10 ns; Input <= X"4e20cd47"; wait for 10 ns; Input <= X"5a9ad5d9"; wait for 10 ns; Input <= X"512c0c03"; wait for 10 ns; Input <= X"ea857ccd"; wait for 10 ns; Input <= X"4cc1d30f"; wait for 10 ns; Input <= X"8891a8a1"; wait for 10 ns; Input <= X"a6b7aadb"; wait for 10 ns; InputEnable <= '0'; wait for 10000 ns; -- numbers are generated with Clk end process; end Testbench; ************************************************************************ " Regards, Jaideep> > > > Also how to generate Random Number's in VHDL? > > > > > > Thanks > > > > Rgds > > > > Macie > > For random numbers try this package: > > http://www.janick.bergeron.com/wtb/packages/random1.vhd > > MPJB
Reply by ●September 19, 20032003-09-19
For simulation or for mapping into hardware? MACEI'S wrote:> Hi guys, > > Does anybody have any idea or any link or code for Additive White > Gaussian Noise in VHDL ? Or any body have written it or not ? > > Also how to generate Random Number's in VHDL? > > Thanks > > Rgds > > Macie-- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759
Reply by ●October 7, 20032003-10-07
This is a multi-part message in MIME format. --------------022DC0C71B68D4FA5FCD0516 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Macie, Xilinx offers an AWGN core that includes the VHDL source code. See the following link for further details: http://www.xilinx.com/ipcenter/catalog/search/logicore/xilinx_awgn.htm Regards, Ed Hemphill MACEI'S wrote:> Hi guys, > > Does anybody have any idea or any link or code for Additive White > Gaussian Noise in VHDL ? Or any body have written it or not ? > > Also how to generate Random Number's in VHDL? > > Thanks > > Rgds > > Macie--------------022DC0C71B68D4FA5FCD0516 Content-Type: text/x-vcard; charset=us-ascii; name="edwin.hemphill.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Ed Hemphill Content-Disposition: attachment; filename="edwin.hemphill.vcf" begin:vcard n:Hemphill;Ed tel;work:801-424-2497 x-mozilla-html:FALSE org:Digital Signal Processing Group;Intellectual Property Solutions Division version:2.1 email;internet:edwin.hemphill@xilinx.com title:Staff Product Applications Engineer adr;quoted-printable:;;4505 Wasatch Blvd, Suite 205=0D=0A;Salt Lake City;Utah;84124;USA fn:Ed Hemphill end:vcard --------------022DC0C71B68D4FA5FCD0516--